поискавой системы для электроныых деталей |
|
TMP101NA250 датащи(PDF) 10 Page - Texas Instruments |
|
TMP101NA250 датащи(HTML) 10 Page - Texas Instruments |
10 / 19 page TMP100 TMP101 SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007 www.ti.com 10 TIMING DIAGRAMS The TMP100 and TMP101 are I2C and SMBus compatible. Figure 5 to Figure 8 describe the various operations on the TMP100 and TMP101. Bus definitions are given below. Parameters for Figure 5 are defined in Table 13. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave. Table 13. Timing Diagram Definitions PARAMETER FAST MODE HIGH-SPEED MODE UNITS PARAMETER MIN MAX MIN MAX UNITS SCLK Operating Frequency f(SCLK) 0.4 3.4 MHz Bus Free TIme Between STOP and START Conditions t(BUF) 600 160 ns Hold time after repeated START condition. After this period, the first clock is generated. t(HDSTA) 600 160 ns Repeated START Condition Setup Time t(SUSTA) 600 160 ns STOP Condition Setup Time t(SUSTO) 600 160 ns Data HOLD Time t(HDDAT) 0 0 ns Data Setup Time t(SUDAT) 100 10 ns SCLK Clock LOW Period t(LOW) 1300 160 ns SCLK Clock HIGH Period t(HIGH) 600 60 ns Clock/Data Fall Time tF 300 160 ns Clock/Data Rise Time tR 300 160 ns for SCLK ≤ 100kHz tR 1000 ns |
Аналогичный номер детали - TMP101NA250 |
|
Аналогичное описание - TMP101NA250 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |