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TPIC44L01DB датащи(PDF) 11 Page - Texas Instruments

номер детали TPIC44L01DB
подробное описание детали  4-CHAMMEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
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TPIC44L01DB датащи(HTML) 11 Page - Texas Instruments

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TPIC44L01, TPIC44L02, TPIC44L03
4CHANNEL SERIAL AND PARALLEL LOW SIDE PREFET DRIVER
SLIS062B NOVEMBER 1996 – REVISED AUGUST 2001
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
serial data operation (continued)
Data is shifted out of SDO on the falling edge of SCLK. The MSB of fault data is available after CS is transitioned
low. The remaining 3 bits of fault data are shifted out in the following three clock cycles. Fault data is latched
into the serial register when CS is transitioned low. A fault must be present on the high to low transition of CS
to be captured by the device. The CS input must be transitioned to a high state after the last bit of serial data
has been clocked into the device. The rising edge of CS inhibits SDI, puts SDO into a high-impedance state,
latches the 4 bits of serial data into the output control register, and clears and reenable the serial fault registers
(see Figure 13). When a shorted-load condition occurs with the TPIC44L01 or TPIC44L03, then the controller
must disable and reenable the channel to clear the fault register and FLT. The TPIC44L02 automatically retries
the output and the fault clears after the fault condition has been corrected.
12
3
4
3-State
FLT3
FLT2
FLT1
FLT0
IN3
3-State
SCLK
CS
SDO
Figure 13
parallel input data operation
In addition to the serial interface, the TPIC44L01, TPIC44L02, and TPIC44L03 also provides a parallel interface
to the microcontroller. The output turns on when either the parallel or the serial interface commands it to turn
on. The parallel data terminals are real-time control inputs for the output drivers. SCLK and CS are not required
to transfer parallel input data to the output buffer. Fault data must be read over the serial data bus as described
in the serial data operation section of this data sheet. The parallel input must be transitioned low and then high
to clear and reenable a gate output after it has been disabled due to a shorted-load fault condition.


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