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TPIC84000TPWPRQ1 датащи(PDF) 10 Page - Texas Instruments |
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TPIC84000TPWPRQ1 датащи(HTML) 10 Page - Texas Instruments |
10 / 29 page TPIC84125-Q1 SLDS175 – AUGUST 2010 www.ti.com IFAULT Flag: Energy Limiting Scheme Two types of output device energy limiting schemes are used: 1. Detection of DC currents flowing in the output transistors In normal operation, with an AC coupled load, continuous DC currents of greater than several mA will not flow in the output transistors. If a current greater than 150mA (nominal) flows in either output transistor for a duration greater than 4ms then the IFAULT condition will be activated and that channel will be placed in tri-state. The exact time before the IFAULT is activated is a function of the voltage across the transistor conducting >150mA load current. Larger voltages across this transistor will cause the deglitch time to be shorter. With VS = 38V and with the output at VS/2 the minimum deglitch time is 4ms. The deglitch timer is reset when the current level falls below 150mA. 2. Detection of excess bi-directional peak currents flowing in the output transistors If a current greater than 0.9A flows in both output transistors when the sine wave signal is driven through the output transistors, then the IFAULT condition will be activated and that channel will be placed in tri-state. The IFAULT condition is activated when both high side and low side transistors have conducted >0.9A at any time during the sine wave burst. The IFAULT signal will be activated immediately when the second output transistor current exceeds 0.9A. The high side and low side detectors are reset during the transmission of a "0" bit. IFAULT has no impact on the operating mode. • If the device is in WAKE-UP mode, the "IFAULT" and "failure" flags are set to 1 in the CSR and the channel which has failed is put in tri-state. • If the device is in SLEEP mode, no SPI flag is updated. However the data buffer will continue to be read out until software stops the data buffer read by sending new Configuration data. SPI Interface A Serial Peripheral Interface (SPI) circuit is integrated into the device to set various internal registers and read out current measurement and status information from the drivers. TPIC84125 operates in slave mode and the microcontroller always acts as a master. The interface to the external micro-controller consists of 4 pins: NCS, SCLK, SDO and SDI. SPI Frame Structure Each SPI communication frame for the TPIC84125 has a length of 64 bits, where it is forbidden to send more than 64 bits. Each 64bit frame consists of 8 command-bits and 56-data-bits. The format of the 64 bits entering at SDI and sent out at SDO is shown in Figure 5: Figure 5. SPI Frame Structure The MSB is the first "in" at the SDI and first "out" at the SDO, where the command sent out on SDO is the command that was sent in the SDI's previous cycle When NCS is high, any signals at the SCLK and SDI pins are ignored, and the SDO is forced into a high impedance state. During a High to Low transition on NCS, the SPI response word is loaded into a shift register, where the SCLK pin must be low when NCS goes low. At each rising edge of SCLK after NCS goes low, the response bit is serially shifted out on the SDO pin. Further, the Control and Status register has to be cleared after readout at next NCS falling edge. 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPIC84125-Q1 |
Аналогичный номер детали - TPIC84000TPWPRQ1 |
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Аналогичное описание - TPIC84000TPWPRQ1 |
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