ISL12022M

7

FN6668.9

June 20, 2012

START Condition Setup Time

SCL rising edge to SDA falling

edge. Both crossing 70% of

600

ns

START Condition Hold Time

From SDA falling edge

falling edge crossing 70% of

600

ns

Input Data Setup Time

From SDA exiting the 30% to

rising edge crossing 30% of

100

ns

Input Data Hold Time

From SCL falling edge

entering the 30% to 70% of

20

900

ns

STOP Condition Setup Time

From SCL rising edge

rising edge crossing 30% of

600

ns

STOP Condition Hold Time

From SDA rising edge to SCL

falling edge. Both crossing

600

ns

Output Data Hold Time

From SCL falling edge

SDA enters the 30% to 70%

0

ns

SDA and SCL Rise Time

20 + 0.1 x Cb

300

ns

13, 14

SDA and SCL Fall Time

20 + 0.1 x Cb

300

ns

13, 14

Cb

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

10

400

pF

13, 14

SDA and SCL Bus Pull-up Resistor

Off-chip

Maximum is determined by

For Cb = 400pF, max is about

2kΩ~2.5kΩ.

For Cb = 40pF, max is about

15kΩ~20kΩ

1

kΩ

13, 14

NOTES:

7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

8. Specified at +25°C.

13. Limits should be considered typical and are not production tested.

16. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only.

17. Defined as the deviation from a target oscillator frequency of 32,768.0Hz at room temperature.

Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 7)

TYP

(Note 8)

MAX

(Note 7)

UNITS

NOTES