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ADF7902BRUZ1 датащи(PDF) 5 Page - Analog Devices |
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ADF7902BRUZ1 датащи(HTML) 5 Page - Analog Devices |
5 / 12 page ADF7902 Rev. 0 | Page 5 of 12 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Rx_DATA CREG2 TEST VBAT2 CE GND1 CH1_SEL CLKOUT CH2_SEL CH3_SEL CLKOUT_ENB CPOUT VCOIN GND2 CVCO RSET LNA_RSET LNA_1 LNA_2 CREG1 VBAT1 OSC1 OSC2 GND1B ADF7902 TOP VIEW (Not to Scale) 1 2 3 4 5 24 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 CREG2 A 0.1 μF capacitor should be added at CREG2 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but may cause higher spurs. 2 TEST Test Output Pin. Leave as no connect. 3 VBAT2 5 V Power Supply for RF Circuitry. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 4 CE Chip Enable Input. Driving CE low puts the part into power-down mode, drawing <1 μA. 5 Rx_DATA Receiver Output. Demodulated data appears on this pin. 6 GND1 Ground for Digital Circuitry. 7 CH1_SEL Channel Select Pin. This represents the LSB of the channel select pins. 8 CH2_SEL Channel Select Pin. 9 CLKOUT Square Wave Clock Output at the Crystal Frequency. This can be used to drive the OSC2 pin of a partnering ADF7902. The output has a 50:50 mark-space ratio and switches between 0 V and 2.2 V. If CLKOUT is disabled by setting Pin 11 high, then CLKOUT must be tied low. 10 CH3_SEL Channel Select Pin. 11 CLKOUT_ENB CLKOUT Enable Input. This should be driven low to enable the reference clock signal to appear on the CLKOUT pin. Driving the pin high removes the clock signal on CLKOUT. It should be driven high when an external reference is used. 12 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 13 GND1B Ground for Digital Circuitry. 14 OSC2 The reference crystal should be connected between this pin and OSC1. The necessary crystal load capacitor should be tied between this pin and ground. A square wave signal can be applied to this pin as an external reference source. 15 OSC1 The reference crystal should be connected between this pin and OSC2. The necessary crystal load capacitor should be tied between this pin and ground. This pin should be connected to ground when OSC2 is driven by an external reference. 16 VBAT1 5 V Power Supply for Digital Circuitry. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 17 CREG1 A 0.1 μF capacitor should be added at CREG1 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but may cause higher spurs. 18 LNA_2 LNA Input. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. 19 LNA_1 Complementary LNA Input. 20 LNA_RSET External Bias Resistor for LNA. A value of 1.1 k Ω is recommended. 21 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. A value of 3.6 k Ω is recommended. 22 CVCO Voltage Controlled Oscillator (VCO) Capacitor. A 22 nF capacitor should be placed between this pin and CREG2 to reduce VCO noise. 23 GND2 Ground for RF Circuitry. 24 VCOIN The tuning voltage on this pin determines the output frequency of the VCO. The higher the tuning voltage, the higher the output frequency. The output of the loop filter is connected here. |
Аналогичный номер детали - ADF7902BRUZ1 |
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Аналогичное описание - ADF7902BRUZ1 |
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