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DAC2815AP датащи(PDF) 8 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
номер детали DAC2815AP
подробное описание детали  DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER 8-Bit Port Interface
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производитель  BURR-BROWN [Burr-Brown (TI)]
домашняя страница  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

DAC2815AP датащи(HTML) 8 Page - Burr-Brown (TI)

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®
DAC2 815
8
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
All digital inputs of the DAC2815 are TTL and 5V CMOS
compatible. Input codes for the DAC2815 are either USB
(Unipolar Straight Binary) or BOB (Bipolar Offset Binary)
depending on the mode of operation. See Figure 3 for
±10V
bipolar connection. See Figures 4 and 5 for 0 to 10V and 0
to –10V unipolar connections.
INTEGRAL OR RELATIVE LINEARITY
This term, also known as end point linearity, describes the
transfer function of analog output to digital input code.
Integral linearity error is the deviation of the analog output
versus code transfer function from a straight line drawn
through the end points.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1
LSB change in the output voltage when the input code
changes by 1 LSB. A differential nonlinearity specification
of
±1 LSB maximum guarantees monotonicity.
UNIPOLAR OFFSET ERROR
The output voltage for code 000
HEX when the DAC is in the
unipolar mode of operation.
BIPOLAR ZERO ERROR
The output voltage for code 800
HEX
when the DAC is in the
bipolar mode of operation.
GAIN ERROR
The deviation of the output voltage span (V
MAX – VMIN) from
the ideal span of 10V – 1 LSB (unipolar mode) or 20V – 1
LSB (bipolar mode). The gain error is specified with and
without the internal +10V reference error included.
OUTPUT SETTLING TIME
The time required for the output voltage to settle within a
percentage-of-full-scale error band for a full scale transition.
Settling to
±0.012% (1/2 LSB) is specified for the DAC2815.
UNIPOLAR AND BIPOLAR
OUTPUTS FOR SELECTED INPUT
DIGITAL INPUT
UNIPOLAR (USB)
BIPOLAR (BOB)
FFF
HEX
+Full scale
+Full scale
800
HEX
+1/2 Full scale
Zero
7FF
HEX
+1/2 Full scale – 1 LSB
Zero – 1 LSB
000
HEX
Zero
–Full scale
DIGITAL-TO-ANALOG GLITCH
Ideally, the DAC output would make a clean step change in
response to an input code change. In reality, glitches occur
during the transition. See Typical Performance Curves.
DIGITAL CROSSTALK
Digital crosstalk is the glitch impulse measured at the output
of one DAC due to a full scale transition on the other
DAC—see Typical Performance Curves. It is dominated by
digital coupling. Also, the integrated area of the glitch pulse
is specified in nV–s. See table of electrical specifications.
DIGITAL FEEDTHROUGH
Digital feedthrough is the noise at a DAC output due to
activity on the digital inputs—see Typical Performance
Curves.
OPERATION
Depending on the address selected, the 4 MSBs or the 8
LSBs are written into the appropriate input register for each
DAC when the WR signal is brought low. This data is
latched in the input register when the WR goes high. Data
are then transferred from the input registers to the DAC latch
registers by bring LE low. The data are latched in the DAC
latch registers when LE goes high. Both DACs are updated
simultaneously.
When CLR is brought low, the input registers are cleared to
000
HEX (–10V), while the DAC registers = 800HEX. If LE is
brought low, the DACs are updated with 000
HEX
resulting in
–10V (bipolar) or 0V (unipolar) on the output.
CIRCUIT DESCRIPTION
Each of the two DACs in the DAC2815 consists of a CMOS
logic section, a CMOS DAC cell, and an output amplifier.
One buried-zener +10.0V reference and a reference inverter
(for a –10.0V reference) are shared by both DACs.
Figure 1 is a simplified circuit for a DAC cell. An R, 2R
ladder network is driven by a voltage reference at V
REF
.
Current from the ladder is switched either to I
OUT or AGND
by 12 single-pole double-throw CMOS switches. This main-
tains constant current in each leg of the ladder regardless of
FIGURE 1. Simplified Circuit Diagram of DAC Cell.
D11
(MSB)
D10
D9
D0
(LSB)
AGND
I
RR
R
2R
2R
2R
2R
2R
R
OUT
V
REF
R
FB


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