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CAT25C64S16I-TE13 датащи(PDF) 6 Page - Catalyst Semiconductor |
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CAT25C64S16I-TE13 датащи(HTML) 6 Page - Catalyst Semiconductor |
6 / 9 page 6 CAT25C64/128 Doc. No. 25069-00 6/99 SPI-1 Advance Information After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continu- ing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address (1FFFh for 25C64 and 3FFFh for 25C128) is reached, the address counter rolls over to 0000h allow- ing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. Figure 2. WREN Instruction Timing Figure 3. WRDI Instruction Timing DEVICE OPERATION Write Enable and Disable The CAT25C64/128 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C64/128, fol- lowed by the 16-bit address(the three Most Significant Bits are don’t care for 25C64 and two most significant bits are don't care for 25C128). SK SI CS SO 0000 0 1 1 0 HIGH IMPEDANCE SK SI CS SO 0000 0 1 0 0 HIGH IMPEDANCE |
Аналогичный номер детали - CAT25C64S16I-TE13 |
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Аналогичное описание - CAT25C64S16I-TE13 |
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