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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS51031YD8 датащи(PDF) 4 Page - Cherry Semiconductor Corporation |
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CS51031YD8 датащи(HTML) 4 Page - Cherry Semiconductor Corporation |
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4 / 8 page  4 Block Diagram G5 COSC CS VREF VC VGATE PGnd VFB Gnd R S 2.5V 1.5V 1.25V 1.15V Q F2 G2 G1 A1 A6 RG VCC 3.3V VCCOK A3 2.4V G3 VREF = 3.3V A2 2.5V 1.5V IC 7IC VREF VCC + - IT + Q IT 5 IT 55 G4 Fault Comp + - + - A4 0.7V 2.3V Q R Q S F1 Slow Discharge Comparator Slow Discharge Flip-Flop CS Charge Sense Comparator CS Comparator Oscillator Comparator VFB Comparator VGATE Flip-Flop Hold Off Comp Control Scheme The CS51031 monitors and the output voltage to determine when to turn on the PFET. If VFB falls below the internal reference voltage of 1.25V during the oscillatorÕs charge cycle, the PFET is turned on and remains on for the dura- tion of the charge time. The PFET gets turned off and remains off during the oscillatorÕs discharge time with the maximum duty cycle to 80%. It requires 7mV typical, and 20mV maximum ripple on the VFB pin is required to oper- ate. This method of control does not require any loop sta- bility compensation. Startup The CS51031 has an externally programmable soft start fea- ture that allows the output voltage to come up slowly, pre- venting voltage overshoot on the output. At startup, the voltage on all pins is zero. As VCC rises, the VC voltage along with the internal resistor RG keeps the PFET off. As VCC and VC continue to rise, the oscillator capacitor (COSC ) and the Soft start/Fault Timing capacitor (CS) charges via internal current sources. COSC gets charged by the current source IC and CS gets charged by the IT source combination described by: ICS = IT - ( + ). The internal Holdoff Comparator ensures that the external PFET is off until VCS > 0.7V, preventing the GATE flip-flop (F2) from being set. This allows the oscillator to reach its operating frequency before enabling the drive output. Soft start is obtained by clamping the VFB comparatorÕs (A6) reference input to approximately 1/2 of the voltage at the CS pin during startup, permitting the control loop and the output voltage to slowly increase. Once the CS pin charges above the Holdoff Comparator trip point of 0.7V, the low feedback to the VFB Comparator sets the GATE flip-flop during COSC Õs charge cycle. Once the GATE flip-flop is set, VGATE goes low and turns on the PFET. When VCS exceeds IT 5 IT 55 Theory of Operation Circuit Description Figure 1: Block Diagram for CS51031 |
Аналогичный номер детали - CS51031YD8 |
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Аналогичное описание - CS51031YD8 |
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