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CS22210 датащи(PDF) 10 Page - Cirrus Logic |
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CS22210 датащи(HTML) 10 Page - Cirrus Logic |
10 / 31 page CS22210 PCI/USB Wireless Controller 10 of 31 D556PP2 Rev. 3.0 www.cirrus.com nSMWE Output Write enable is used in combination with nSMRAS, nSMCAS, and nSMWE to specify whether the current cycle is a read or a write cycle. Also used during reset to latch in the strap value for tst_bypass; if set to a '1' implies PLL bypass. Also shared as the ROMWE to do flash programming. SMDQM[1:0] Output Data mask bit 1:0. These signals function as byte enable lines masking unwanted bytes on memory writes. Also used as testmode(1:0) when NTEST pin is '0'. SMCKE Output Clock enable. SMCKE is used to enable and disable clocking of internal RAM logic. SMA0 Output Address bit0. The address bus specifies either the row address or column address. Also shared as boot-rom address bit0. This pin should be pull- down. SMA1 Output Address bit1. Also shared as boot-rom address bit1. Also used during reset to latch in the strap value for pcisel; if set to a '1' implies pci mode. SMA2 Output Address bit2. Also shared as boot-rom address bit2. Also used during reset to latch in the strap value for usbsel; if set to a '1' implies usb mode. SMA3 Output Address bit3. Also shared as boot-rom address bit3. This pin should be pull-down. SMA4 Output Address bit4. Also shared as boot-rom address bit4. Also used during reset to latch in the strap value for romcfg; if set to a '1' implies pci configuration data should be downloaded from ROM. SMA5 Output Address bit5. Also shared as boot-rom address bit5. Also used during reset to latch in the strap value for test_rst_enb; if set to a '0' implies normal operation mode. |
Аналогичный номер детали - CS22210 |
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Аналогичное описание - CS22210 |
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