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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS5126 датащи(PDF) 9 Page - Cirrus Logic |
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CS5126 датащи(HTML) 9 Page - Cirrus Logic |
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9 / 32 page  rithm. The worst-case codes for dynamic errors are the major transitions (1/2 FS; 1/4, 3/4 FS; etc.). Since DNL effects are most critical with low-level signals, the codes around in mid-scale, (that is, 1/2 FS), are most important. Yet those codes are worst-case for dynamic DNL errors! With all linearity calibration performed on-chip to 18-bits, the CS5126 maintains accurate bit weights. DNL errors are dominated by residual calibration errors of ±1/4 LSB rather than dy- namic errors in the comparator. Furthermore, all DNL effects on S/(N+D) are buried by white broadband noise. This yields excellent sound quality independent of signal level. (See Figure 5) Sampling Distortion Like most discrete sample/hold amplifier de- signs, the CS5126’s inherent sample/hold exhib- its a frequency-dependent distortion due to nonideal sampling of the analog input voltage. The calibrated capacitor array used during con- versions is also used to track and hold the ana- log input signal. The conversion is not per- formed on the analog input voltage per se, but is actually performed on the charge trapped on the capacitor array at the moment the HOLD com- mand is given. The charge on the array ideally assumes a linear relationship to the analog input voltage. Any deviation from this linear relation- ship will result in conversion errors even if the conversion process proceeds flawlessly. At dc, the DAC capacitor array’s voltage coeffi- cient dictates the converter’s linearity. This vari- ation in capacitance with respect to applied sig- nal voltage yields a nonlinear relationship be- tween the charge on the array and the analog in- put voltage and places a bow or wave in the transfer function. This is the dominant source of distortion at low input frequencies (Figure 4). The ideal relationship between the charge on the array and the input voltage can also be distorted at high signal frequencies due to nonlinearities in the internal MOS switches. Dynamic signals cause ac current to flow through the switches connecting the capacitor array to the analog in- put pin in the track mode. Nonlinear on-resis- tance in the switches causes a nonlinear voltage drop. This effect worsens with increased signal frequency and slew rate as shown in Figure 6 since the magnitude of the steady state current increases. First noticeable at 1kHz, this distor- tion assumes a linear relationship with input fre- quency. With signals 20dB or more below full- scale, it no longer dominates the converter’s overall S/(N+D) performance. This distortion is strictly an ac sampling phe- nomenon. If significant energy exists at high fre- quencies, the effect can be eliminated using an external track-and-hold amplifier to allow the ar- ray’s charge current to decay, thereby eliminat- ing any voltage drop across the switches. Since the CS5126 has a second sampling function on- chip, the external track-and-hold can return to the track mode once the converter’s HOLD input falls. It need only acquire the analog input by the time the entire conversion cycle finishes. Analog Input Frequency 5kHz 10kHz 15kHz 20kHz 25kHz 0.020 0.012 0.008 0.004 0 0.016 Figure 6. THD vs Input Frequency ( 9V p-p Full-Scale Input) CS5126 DS32F1 9 |
Аналогичный номер детали - CS5126 |
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Аналогичное описание - CS5126 |
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