ISL29033

5

FN7656.2

February 25, 2013

SCL and SDA Input Low Voltage

0.55

V

SCL and SDA Input High Voltage

1.25

V

SDA Current Sinking Capability

4

5

mA

INT Current Sinking Capability

4

5

mA

NOTES:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

7. A 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count as a fluorescent light with

illuminance at the stated lux.

8. An 850nm IR LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count as solar light with

illuminance at the stated lux.

and 1MΩ 1% tolerance.

PARAMETER

DESCRIPTION

CONDITION

MIN

(Note 6)

TYP

MAX

(Note 6)

UNIT

1.7

3.63

V

SCL Clock Frequency

400

kHz

SCL and SDA Input Low Voltage

0.55

V

SCL and SDA Input High Voltage

1.25

V

Hysteresis of Schmitt Trigger Input

V

Low-level Output Voltage (Open-drain) at 4mA Sink

Current

0.4

V

Input Leakage for each SDA, SCL Pin

-10

10

µA

Pulse Width of Spikes that must be Suppressed by

the Input Filter

50

ns

SCL Falling Edge to SDA Output Data Valid

900

ns

Capacitance for each SDA and SCL Pin

10

pF

Hold Time (Repeated) START Condition

After this period, the first clock pulse

is generated.

600

ns

LOW Period of the SCL Clock

1300

ns

HIGH Period of the SCL Clock

600

ns

Set-up Time for a Repeated START Condition

600

ns

Data Hold Time

30

ns

Data Set-up Time

100

ns

Rise Time of both SDA and SCL Signals

(Note 9)

20 +

ns

Fall Time of both SDA and SCL Signals

(Note 9)

20 +

ns

Set-up Time for STOP Condition

600

ns

Bus Free Time Between a STOP and START

Condition

1300

ns

Capacitive Load for Each Bus Line

400

pF

SDA and SCL System Bus Pull-up Resistor

1kΩ

PARAMETER

DESCRIPTION

CONDITION

MIN

(Note 6)

TYP

MAX

(Note 6)

UNIT