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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FM3164 датащи(PDF) 7 Page - Cypress Semiconductor |
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FM3164 датащи(HTML) 7 Page - Cypress Semiconductor |
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7 / 33 page  FM3164/FM31256 Document Number: 001-86391 Rev. *C Page 7 of 33 The comparator is a general purpose device and its application is not limited to the NMI function. The comparator is not integrated into the special function registers except as it shares its output pin with the CAL output. When the RTC calibration mode is invoked by setting the CAL bit (register 00h, bit 2), the CAL/PFO output pin will be driven with a 512 Hz square wave and the comparator will be ignored. Since most users only invoke the calibration mode during production, this should have no impact on system operations using the comparator. Note The maximum voltage on the comparator input PFI is limited to 3.75 V under normal operating conditions. Event Counter The FM3164/FM31256 offers the user two battery-backed event counters. Input pins CNT1 and CNT2 are programmable edge detectors. Each clocks a 16-bit counter. When an edge occurs, the counters will increment their respective registers. Counter 1 is located in registers 0Dh and 0Eh, Counter 2 is located in registers 0Fh and 10h. These register values can be read anytime VDD is above VTP, and they will be incremented as long as a valid VBAK power source is provided. To read, set the RC bit (register 0Ch, bit 3) to 1. This takes a snapshot of all four counter bytes allowing a stable value even if a count occurs during the read. The registers can be written by software allowing the counters to be cleared or initialized by the system. Counts are blocked during a write operation. The two counters can be cascaded to create a single 32-bit counter by setting the CC control bit (register 0Ch, bit 2). When cascaded, the CNT1 input will cause the counter to increment. CNT2 is not used in this mode and should be tied to ground. The control bits for event counting are located in register 0Ch. Counter 1 Polarity is bit C1P, bit 0; Counter 2 Polarity is C2P, bit 1; the Cascade Control is CC, bit 2; and the Read Counter bit is RC, bit 3. The polarity bits must be set prior to setting the counter value(s). If a polarity bit is changed, the counter may inadvertently increment. If the counter pins are not being used, tie them to ground. Serial Number A memory location to write a 64-bit serial number is provided. It is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. The 8 bytes of data and the lock bit are all accessed via the device ID for the Processor Companion. Therefore the serial number area is separate and distinct from the memory array. The serial number registers can be written an unlimited number of times, so these locations are general purpose memory. However, once the lock bit is set, the values cannot be altered and the lock cannot be removed. Once locked the serial number registers can still be read by the system. The serial number is located in registers 11h to 18h. The lock bit is SNL (register 0Bh, bit 7). Setting the SNL bit to a ‘1’ disables writes to the serial number registers, and the SNL bit cannot be cleared. Real-time Clock Operation The real-time clock (RTC) is a timekeeping device that can be battery or capacitor backed for permanently-powered operation. It offers a software calibration feature that allows high accuracy. The RTC consists of an oscillator, clock divider, and a register system for user access. It divides down the 32.768 kHz time-base and provides a minimum resolution of seconds (1 Hz). Static registers provide the user with read/write access to the time values. It includes registers for seconds, minutes, hours, day-of-the-week, date, months, and years. A block diagram (Figure 7) illustrates the RTC function. The user registers are synchronized with the timekeeper core using R and W bits in register 00h described below. Changing the R bit from ‘0’ to ‘1’ transfers timekeeping information from the core into holding registers that can be read by the user. If a timekeeper update is pending when R is set, then the core will be updated prior to loading the user registers. The registers are frozen and will not be updated again until the R bit is cleared to ‘0’. R is used for reading the time. Setting the W bit to ‘1’ locks the user registers. Clearing it to ‘0’ causes the values in the user registers to be loaded into the timekeeper core. W bit is used for writing new time values. Users should be certain not to load invalid values, such as FFh, to the timekeeping registers. Updates to the timekeeping core occur continuously except when locked. Figure 6. Event Counter 16-bit Counter CNT1 CC CNT2 C1P C2P 16-bit Counter |
Аналогичный номер детали - FM3164 |
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Аналогичное описание - FM3164 |
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