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TSB83AA22A датащи(PDF) 4 Page - Texas Instruments

номер детали TSB83AA22A
подробное описание детали  IEEE Std 1394b-2002 Phy and OHCI Link Device
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TSB83AA22A датащи(HTML) 4 Page - Texas Instruments

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TSB83AA22A
SLLA255 – APRIL 2006
Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators
to
monitor
the
line
states
during
initialization
and
arbitration
when
connected
to
an
IEEE
Std
1394a-2000-compliant device. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during IEEE Std 1394a-2000-mode arbitration and sets the speed of the next
packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the
TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage.
When connected to an IEEE Std 1394a-2000-compliant node, the TSB83AA22A Phy section provides a 1.86-V
nominal bias voltage at the TPBIAS terminal for port termination. The Phy section contains two independent
TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver,
indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter
capacitor of 1
µF.
The line drivers in the TSB83AA22A Phy section are designed to work with external 112-
Ω termination resistor
networks in order to match the 110-
Ω cable impedance. One termination network is required at each end of a
twisted-pair cable. Each network is composed of a pair of series-connected 56-
Ω resistors. The midpoint of the
pair of resistors that is connected to the TPA terminals is connected to its corresponding TPBIAS voltage
terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground
through a parallel RC network with recommended values of 5 k
Ω and 270 pF. The values of the external
line-termination resistors are selected to meet the standard specifications when connected in parallel with the
internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the
driver output current, along with other internal operating currents.
When the power supply of the TSB83AA22A is off while the twisted-pair cables are connected, the
TSB83AA22A transmitter and receiver circuitry present to the cable a high-impedance signal that does not load
the device at the other end of the cable.
When the TSB83AA22A Phy section is used without one or more of the ports brought out to a connector, the
twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the
port must be forced to the IEEE Std 1394a-2000-only mode (data-strobe-only mode), after which the TPB+ and
TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be
connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can
be left unconnected. The TPBIAS terminal can be connected through a 1-
µF capacitor to ground or left
unconnected.
The TESTM, TESTW, SE, and SM terminals are used to set up various manufacturing test conditions. For
normal operation, the TESTM and TESTW terminals must be connected to VDD through a 1-k
Ω resistor. The
SE and SM terminals must be tied to ground through a 1-k
Ω resistor.
Three package terminals are used as inputs to set the default value for three configuration status bits in the
self-ID packet. They can be pulled high through a 1-k
Ω resistor or hardwired low as a function of the equipment
design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for
power from the cable or the ability to supply power to the cable). The contender bit in the Phy register set
indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus
manager (BM). On the TSB83AA22A, this bit can only be set by a write to the Phy register set. If a node is to be
a contender for IRM or BM, then the node software must set this bit in the Phy register set.
The LPS (link power status) terminal of the Phy section works with the LKON terminal to manage the power
usage in the node. The PHY_LPS signal from the LLC section is used in conjunction with the LCtrl bit (see Table
1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC
section. The LPS signal also resets, disables, and initializes the Phy section–LLC section interface (the state of
the PHY section–LLC section interface is controlled solely by the LPS input regardless of the state of the LCtrl
bit). The LPS terminal of the Phy section must be connected to the PHY_LPS terminal of the LLC section during
normal operation.
4
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