поискавой системы для электроныых деталей |
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TSB83AA22A датащи(PDF) 5 Page - Texas Instruments |
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TSB83AA22A датащи(HTML) 5 Page - Texas Instruments |
5 / 7 page www.ti.com TSB83AA22A SLLA255 – APRIL 2006 The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the Phy section detects that the LPS input is inactive, the PHY section–LLC section interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the Phy section–LLC section interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB83AA22A continues the necessary Phy repeater functions required for normal network operation regardless of the state of the Phy section–LLC section interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the Phy section initializes the interface and returns to normal operation. The Phy section–LLC section interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB83AA22A issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the Phy section and LLC section now being accessible). The Phy section uses the LKON terminal to notify the LLC section to power up and become active. When activated, the output LKON signal is a square wave. The Phy section activates the LKON output when the LLC section is inactive and a wake-up event occurs. The LLC section is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on Phy packet addressed to this node is received, or conditionally when a Phy interrupt occurs. The Phy section deasserts the LKON output when the LLC section becomes active (both LPS sensed as active and the LCtrl bit set to 1). The Phy section also deasserts the LKON output when a bus reset occurs, unless a Phy interrupt condition exists which would otherwise cause LKON to be active. If the TSB83AA22A is power cycled and the power class is 0 through 4, then the Phy section asserts LKON for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1. Special Note: This product is for high-volume PC applications only. Contact support@ti.com for more information. 5 Submit Documentation Feedback |
Аналогичный номер детали - TSB83AA22A |
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Аналогичное описание - TSB83AA22A |
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