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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ML2256X-xxxMB датащи(PDF) 5 Page - List of Unclassifed Manufacturers |
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ML2256X-xxxMB датащи(HTML) 5 Page - List of Unclassifed Manufacturers |
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5 / 66 page  FEDL2256X-06 ML22Q563/ML2256X PIN DESCRIPTION (1) Pin Symbol I/O Attribute Description Attribute Initial value 1 AIN I — Speaker amplifier input pin. analog 0 2 SG O — Built-in speaker amplifier’s reference voltage output pin. Connect a capacitor of 0.1 μF or more between this pin and DGND. analog 0 3* 2 VDDR O — 2.5 V regulator output pin. Acts as an internal power supply (for ROM). Connect a capacitor of 10 μF or more between this pin and DGND. analog 0 4,18 DVDD — — Digital power supply pin. Connect a bypass capacitor of 10 μF or more between this pin and DGND. power — 5,15 DGND — — Digital ground pin gnd — 6 VDDL O — 2.5 V regulator output pin. Acts as an internal power supply (for logic). Connect a capacitor of 10 μF or more between this pin and DGND. power 0 7 DIPH I Positive Serial interface switching pin. Pin for choosing between rising edges and falling edges as to the edges of the SCK pulses used for shifting serial data input to the SI pin into the inside of the LSI. When this pin is at a “L” level, SI input data is shifted into the LSI on the rising edges of the SCK clock pulses and a status signal is output from the SO pin on the falling edges of the SCK clock pulses. When this pin is at a “H” level, SI input data is shifted into the LSI on the falling edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock pulses. digital 0 8 STATUS O Positive Channel status output pin. Outputs the BUSYB or NCR signal for each channel by inputting the OUTSTAT command. digital 1 9 ERR O Positive Error output pin. Outputs a “H” level if an error occurs. digital 0 10 CSB I Negative Chip select pin. A “L” level on this pin accepts the SCK or SI inputs. When this pin is at a “H” level, neither the SCK nor SI signal is input to the LSI. digital 1 11 SCK I Positive Synchronous serial clock input pin. clk 0 12 SI I — Synchronous serial data input pin. When the DIPH pin is at a “L” level, data is shifted in on the rising edges of the SCK clock pulses. When the DIPH pin is at a “H” level, data is shifted in on the falling edges of the SCK clock pulses. digital 0 13 SO O Positive Channel status serial output pin. Outputs a status signal on the falling edges of the SCK clock pulses when the DIPH pin is at a ”L” level; outputs a status signal on the rising edges of the SCK clock pulses when the DIPH pin is at a ”H” level. When the CSB pin is at a ”L” level, the status of each channel is output serially in sync with the SCK clock. When the CSB pin is at a ”H” level, this pin goes into a high impedance state. digital Hi-Z 5/66 |
Аналогичный номер детали - ML2256X-xxxMB |
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Аналогичное описание - ML2256X-xxxMB |
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