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IA59032

Data Sheet

32-Bit High Speed Microprocessor Slice

Copyright

© 2000

[_________The End of Obsolescence

™

are the 32 word by 32-bit 2-port RAM and the high-speed ALU.

Data in any of the 32 words of the RAM can be read from the A-port of the RAM as controlled by the 4-bit

A address field input. Likewise, data in any of the 32 words of the RAM as defined by the B address field

input can be simultaneously read from the B-port of the RAM. The same code can be applied to the A select

field and B select field in which case the identical file data will appear at both the RAM A-port and B-port

outputs simultaneously.

When enabled by the RAM write enable (CP low), new data is always written into the file (word) defined by

the B address field of the RAM. The RAM data input field is driven by a 3-input mux. This configuration is

used to shift the ALU output data F if desired. This three-input mux scheme allows the data to be shifted up

one bit position, shifted down one bit position, or not shifted in either direction.

The high speed ALU can perform three binary arithmetic and five logic operations on the two 32-bit input

words R and S. The R input field is driven from a 2-input mux, while the S input field is driven by a 3-input

mux. Both muxes also have an inhibit capability; that is, no data is passed. This is equivalent to a “zero”

source operand.

inputs. Likewise, the ALU S-input mux has the RAM A-port, B-port, and the Q register connected as inputs.

This muxing scheme provides the capability of selecting various pairs of the A, B, D, Q, and zero inputs as

source operands to the ALU. These five inputs, when taken two at a time, result in ten possible

combinations of source operand pairs. The I(2:0) inputs are the microinstruction inputs used to select the

ALU source operands.

The two source operands not fully described as yet are the D input and the Q input. The D input is the 32-

bit wide direct data field input. This port is used to insert all data into the working registers inside the device.

Likewise, this input can be used in the ALU to modify any of the internal data files. The Q register is a

separate 32-bit file intended primarily for multiplication and division routines but it can also be used as an

accumulator or holding register for some applications.

The ALU itself is capable of performing three binary arithmetic and five logic functions. The I(5:3) inputs

are used to select the ALU function.

The ALU has three status-oriented outputs. These are F31, FZERO, and OVR. The F31 output is the most

significant (sign) bit of the ALU and can be used to determine positive or negative results without enabling

the three-state data outputs. F31 is non-inverted with respect to the sign bit output Y(31). The FZERO

output is used for zero detect. It is an open-collector output. FZERO is HIGH when all F outputs are

LOW. The overflow output (OVR) is used to flag arithmetic operations that exceed the available two’s

complement number range. The OVR output is HIGH when overflow exists.

The ALU data output is routed to several destinations. It can be a data output of the device and it can also

be stored in the RAM or the Q register. Eight possible combinations of ALU destination functions are

available, as defined by the I(8:6) inputs.