поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

CD80C86-2 датащи(PDF) 5 Page - Intersil Corporation

номер детали CD80C86-2
подробное описание детали  CMOS 16-Bit Microprocessor
Download  35 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  INTERSIL [Intersil Corporation]
домашняя страница  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD80C86-2 датащи(HTML) 5 Page - Intersil Corporation

  CD80C86-2 Datasheet HTML 1Page - Intersil Corporation CD80C86-2 Datasheet HTML 2Page - Intersil Corporation CD80C86-2 Datasheet HTML 3Page - Intersil Corporation CD80C86-2 Datasheet HTML 4Page - Intersil Corporation CD80C86-2 Datasheet HTML 5Page - Intersil Corporation CD80C86-2 Datasheet HTML 6Page - Intersil Corporation CD80C86-2 Datasheet HTML 7Page - Intersil Corporation CD80C86-2 Datasheet HTML 8Page - Intersil Corporation CD80C86-2 Datasheet HTML 9Page - Intersil Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 35 page
background image
5
FN2957.3
January 9, 2009
TEST
23
I
TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
NMI
17
I
NON-MASKABLE INTERRUPT: An edge triggered input which causes a type 2 interrupt. A subroutine
is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable
internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current
instruction. This input is internally synchronized.
RESET
21
I
RESET: Causes the processor to immediately terminate its present activity. The signal must transition
LOW to HIGH and remain active HIGH for at least 4 clock cycles. It restarts execution, as described
in the “Instruction Set Summary” on page 31 when RESET returns LOW. RESET is internally
synchronized.
CLK
19
I
CLOCK: Provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide optimized internal timing.
VCC
40
VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for
decoupling.
GND
1, 20
GND: Ground. Note: Both must be connected. A 0.1µF capacitor between pins 1 and 20 is
recommended for decoupling.
MN/MX
33
I
MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
Minimum Mode System
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to minimum
mode are described; all other pin functions are as described in the following.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
M/IO
28
O
STATUS LINE: Logically equivalent to S2 in the maximum mode. It is used to distinguish a memory
access from an I/O access. M/lO becomes valid in the t4 preceding a bus cycle and remains valid until
the final t4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic one during local
bus “hold acknowledge”.
WR
29
O
WRITE: Indicates that the processor is performing a write memory or write I/O cycle, depending on
the state of the M/IO signal. WR is active for t2, t3 and tW of any write cycle. It is active LOW, and is
held to high impedance logic one during local bus “hold acknowledge”.
INTA
24
O
INTERRUPT ACKNOWLEDGE: Used as a read strobe for interrupt acknowledge cycles. It is active
LOW during t2, t3 and tW of each interrupt acknowledge cycle. Note that INTA is never floated.
ALE
25
O
ADDRESS LATCH ENABLE: Provided by the processor to latch the address into the 82C82/82C83
address latch. It is a HIGH pulse active during clock LOW of t1 of any bus cycle. Note that ALE is never
floated.
DT/R
27
O
DATA TRANSMIT/RECEIVE: Needed in a minimum system that desires to use a data bus transceiver.
It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN
26
O
DATA ENABLE: Provided as an output enable for a bus transceiver in a minimum system which uses
the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a
read or INTA cycle it is active from the middle of t2 until the middle of t4, while for a write cycle it is
active from the beginning of t2 until the middle of t4. DEN is held to a high impedance logic one during
local bus “hold acknowledge”.
Pin Descriptions (Continued)
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct
multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
80C86


Аналогичный номер детали - CD80C86-2

производительномер деталидатащиподробное описание детали
logo
Intersil Corporation
CD80C88 INTERSIL-CD80C88 Datasheet
246Kb / 32P
   CMOS 8/16-Bit Microprocessor
March 1997
CD80C88-2 INTERSIL-CD80C88-2 Datasheet
246Kb / 32P
   CMOS 8/16-Bit Microprocessor
March 1997
More results

Аналогичное описание - CD80C86-2

производительномер деталидатащиподробное описание детали
logo
OKI electronic componet...
MSM80C86A-10RS OKI-MSM80C86A-10RS Datasheet
269Kb / 37P
   16-Bit CMOS MICROPROCESSOR
logo
Renesas Technology Corp
80C86 RENESAS-80C86 Datasheet
1Mb / 38P
   CMOS 16-Bit Microprocessor
logo
Intersil Corporation
80C86 INTERSIL-80C86 Datasheet
686Kb / 37P
   CMOS 16-Bit Microprocessor
80C86 INTERSIL-80C86_06 Datasheet
804Kb / 37P
   CMOS 16-Bit Microprocessor
80C88 INTERSIL-80C88 Datasheet
246Kb / 32P
   CMOS 8/16-Bit Microprocessor
March 1997
80C88 INTERSIL-80C88_04 Datasheet
620Kb / 32P
   CMOS 8/16-Bit Microprocessor
logo
Renesas Technology Corp
80C88 RENESAS-80C88 Datasheet
1Mb / 39P
   CMOS 8-/16-Bit Microprocessor
logo
Intersil Corporation
80C88 INTERSIL-80C88_08 Datasheet
606Kb / 38P
   CMOS 8-/16-Bit Microprocessor
logo
California Micro Device...
G65SC816 CALMIRCO-G65SC816 Datasheet
115Kb / 2P
   CMOS 8/16-BIT MICROPROCESSOR FAMILY
logo
Intersil Corporation
HS-80C86RH INTERSIL-HS-80C86RH Datasheet
239Kb / 37P
   Radiation Hardened 16-Bit CMOS Microprocessor
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35


датащи скачать

Go To PDF Page


ссылки URL




Конфиденциальность
ALLDATASHEETRU.COM
Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com