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CA3193 датащи(PDF) 6 Page - Intersil Corporation |
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CA3193 датащи(HTML) 6 Page - Intersil Corporation |
6 / 11 page 65 Application Information Circuit Description The block diagram of the CA3193 amplifier shows the voltage gain and supply current for each of its fouramplifier stages. Simplified and complete schematic diagrams of the CA3193 amplifier are shown in Figures 5 and 6, respectively. A quad of physically cross-connected NPN transistors comprise the input-stage differential pair (Q1, Q2 in Figures 5 and 6); this arrangement contributes to the low input offset- voltage characteristics of the amplifier. The ultra-high gain provided in the first stage ensures that subsequent stages cannot significantly influence the overall offset-voltage characteristics of the amplifier. High load impedances for the input-stage differential pair (Q1, Q2) are provided by the cascode-connected PNP transistors Q3, Q5 and Q4, Q6, thereby contributing to the high gain developed in the stage. The second stage of the amplifier consists of a differential amplifier employing PMOS/FETs (Q7, Q8 in Figures 5 and 6) with appropriate drain loading. Since Q7 and Q8 are M0S/FETs, their loading on the first stage is quite low, thereby making an additional contribution to the high gain developed in the first stage. The second stage is also config- ured to convert its differential signal to a single-ended output signal by means of current mirror D9,Q30 (Figures 5 and 6) to drive subsequent gain stage. The third stage of the amplifier consists of Darlington- connected NPN transistors (Q17, Q19 in Figures 5 and 6), driving the quasi-complementary Class AB output stage (Q14 and Q15, Q16 in Figures 5 and 6). Output-stage short- circuit protection is activated by voltage drops developed acrossthe 60 Ω resistors adjacent to the output terminal (R9 and R10, Figure 6). When the voltage drop developed across either of these resistors reaches a potential equal to 1 VBE, the respective protective transistor (Q12 or Q13) is activated and shunts the base drive from the bases of the output stage transistors (Q14 and Q15, Q16). Internal frequency compensation for the CA3193 amplifier is provided by two internal networks, a 6pF capacitor connected between the input-stage transistor collectors and the node between the third and output stagesand a second network, consisting of a 20pF capacitor in series with a 7.5k Ω resistor connected between the input and output nodes of the third stage. Offset Voltage Nulling The input offset voltage can be nulled to zero by any of the three methodsshown in the table below. A 10K potentiome- ter betweenterminals1and5, withits wiper returned toV-, will provide a gross nulling for all types. For finer nulling, either of the other two circuits shown below may be used, thus providing simpler improved resolution for all types. CAUTION: The CA3193 amplifiers will be damaged if they are plugged into op amp circuits employing nulling with respect to the V+ supply bus. Offset Voltage Nulling OFFSET NULLING CIRCUITS TYPE RESISTOR R VALUE RESISTOR R VALUE RESISTOR R VALUE CA3193A 10K 50K 10K CA3193 10K 20K 5K Gross Offset Adjustment Finer Offset Adjustments 1 5 R V- 1 5 10K V- R 1K V- R R 1 5 CA3193, CA3193A |
Аналогичный номер детали - CA3193 |
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Аналогичное описание - CA3193 |
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