Data Sheet

AD7686

TIMING SPECIFICATIONS

−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

See Figure 3 and Figure 4 for load conditions.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

0.5

1.6

µs

Acquisition Time

400

ns

Time Between Conversions

2

µs

CNV Pulse Width ( CS Mode)

10

ns

SCK Period (CS Mode)

15

ns

SCK Period (Chain Mode)

VIO Above 4.5 V

17

ns

VIO Above 3 V

18

ns

VIO Above 2.7 V

19

ns

VIO Above 2.3 V

20

ns

SCK Low Time

7

ns

SCK High Time

7

ns

SCK Falling Edge to Data Remains Valid

5

ns

SCK Falling Edge to Data Valid Delay

VIO Above 4.5 V

14

ns

VIO Above 3 V

15

ns

VIO Above 2.7 V

16

ns

VIO Above 2.3 V

17

ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 4.5 V

15

ns

VIO Above 2.7 V

18

ns

VIO Above 2.3 V

22

ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

25

ns

SDI Valid Setup Time from CNV Rising Edge (CS Mode)

15

ns

SDI Valid Hold Time from CNV Rising Edge (CS Mode)

0

ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

5

ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

5

ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

3

ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

4

ns

SDI High to SDO High (Chain Mode with Busy Indicator)

VIO Above 4.5 V

15

ns

VIO Above 2.3 V

26

ns

500µA

500µA

1.4V

TO SDO

50pF

Figure 3. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

Figure 4. Voltage Levels for Timing

Rev. C | Page 5 of 28