AD9942_15 datasheet(6/36 Pages) AD

номер детали	AD9942

подробное описание детали	Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing Core

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AD9942

Rev. A | Page 6 of 36

CHANNEL-TO-CHANNEL SPECIFICATIONS

TMIN to TMAX, AVDD_X = DVDD_X = 3.0 V, fCLI = 40 MHz, typical timing specifications, unless otherwise noted. X = A, B.

Table 4.

Parameter

Min

Typ

Max

Unit

Notes

CHANNEL A/CHANNEL B OUTPUT

CODE MATCHING ERROR1

<1.0%

VGA = 6 dB, 12 dB, and 18 dB conditions.

CROSSTALK ERROR

VGA = 6 dB, 12 dB, and 18 dB conditions.

Channel A to Channel B

−84

dB

Full-scale step applied to Channel A while

measuring response on Channel B.

Channel B to Channel A

−84

dB

Full-scale step applied to Channel B while

measuring response on Channel A.

1 Matching error calculated using a ramp input applied to Channel A and Channel B simultaneously. Typical Channel A/Channel B error is <1.0% at each output code.

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