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LS7211 датащи(PDF) 8 Page - LSI Computer Systems |
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LS7211 датащи(HTML) 8 Page - LSI Computer Systems |
8 / 8 page FIGURE 10. PROGRAMMABLE FREQUENCY DIVIDER 17 10 11 12 13 14 15 16 18 WB0 WB1 WB2 WB3 WB4 WB5 WB6 WB7 1 2 4 A B TRIG 7 RESET 8 9 OUT Vss ƒo +V ƒi +V 3 LS7212 ƒi ƒo Case 1, Mode = DO; ÷4 ƒo Case 2, Mode = DD; ÷6 CASE 1. MODE = DO or DR; PRESCALE FACTOR, S = 1 In this setup a frequency division of the input clock, ƒi by a factor of 2 to 257, in increments of 1 can be obtained according to the equation: ƒo = where W (weighting factor) = 0 to 255 ƒi W + 2 The ƒo pulse width is non-symmetrical (non-50% duty -cycle) CASE 2. MODE = DD; PRESCALE FACTOR, S = 1 In this setup a frequency division of the input clock, ƒi by a factor of 2 to 512, in increments of 2 can be obtained according to the equation: ƒo = where W (weighting factor) = 0 to 255 ƒi 2(W + 1) The ƒo pulse widths are symmetrical with 50% duty -cycle EXAMPLES OF CASE 1 and CASE 2 FREQUENCY DIVISIONS WITH W = 2 V DD CLOCK |
Аналогичный номер детали - LS7211 |
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Аналогичное описание - LS7211 |
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