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DAC3282 датащи(PDF) 11 Page - Texas Instruments |
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DAC3282 датащи(HTML) 11 Page - Texas Instruments |
11 / 65 page DAC3282 www.ti.com SLAS646C – DECEMBER 2009 – REVISED MAY 2015 6.8 Timing Characteristics over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT (1) ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10.4 ns DAC outputs are updated on the tpd Output propagation delay falling edge of DAC clock. Does not 2 ns include Digital Latency (see below). tr(IOUT) Output rise time 10% to 90% 220 ps tf(IOUT) Output fall time 90% to 10% 220 PS IOUT current settling to 1% of IOUTFS. Measured from SDENB DAC Wake-up Time 90 μs rising edge; Register CONFIG24, toggle sleepa from 1 to 0 Power-up IOUT current settling to less than time 1% of IOUTFS. Measured from DAC Sleep Time SDENB rising edge; Register 90 μs CONFIG24, toggle sleepa from 0 to 1. TIMING LVDS INPUTS: DATACLKP/N, double edge latching – See Figure 25 Setup time, D[7:0]P/N and FRAMEP/N latched on rising edge ts(DATA) FRAMEP/N, valid to either edge of 0 ps of DATACLKP/N only DATACLKP/N Hold time, D[7:0]P/N and FRAMEP/N latched on rising edge th(DATA) FRAMEP/N, valid after either edge 400 ps of DATACLKP/N only of DATACLKP/N fDATACLK is DATACLK frequency in 1/2fDATACL t(FRAME) FRAMEP/N pulse width ns MHz K Maximum offset between FIFO Bypass Mode only 1/2fDACCLK t_align DATACLKP/N and DACCLKP/N fDACCLK is DACCLK frequency in ns –0.55 rising edges MHz TIMING OSTRP/N Input: DACCLKP/N rising edge latching Setup time, OSTRP/N valid to rising ts(OSTR) 200 ps edge of DACCLKP/N Hold time, OSTRP/N valid after th(OSTR) 200 ps rising edge of DACCLKP/N SERIAL PORT TIMING – See Figure 40 and Figure 41 Setup time, SDENB to rising edge of ts(SDENB) 20 ns SCLK Setup time, SDIO valid to rising ts(SDIO) 10 ns edge of SCLK Hold time, SDIO valid to rising edge th(SDIO) 5 ns of SCLK Register CONFIG5 read 1 μs (temperature sensor read) t(SCLK) Period of SCLK All other registers 100 ns Register CONFIG5 read 0.4 μs (temperature sensor read) t(SCLKH) High time of SCLK All other registers 40 ns Register CONFIG5 read 0.4 μs (temperature sensor read) t(SCLKL) Low time of SCLK All other registers 40 ns Data output delay after falling edge td(Data) 10 ns of SCLK tRESET Minimum RESETB pulsewidth 25 ns (1) Measured single ended into 50 Ω load. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DAC3282 |
Аналогичный номер детали - DAC3282_15 |
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Аналогичное описание - DAC3282_15 |
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