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TC500 датащи(PDF) 8 Page - Microchip Technology |
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TC500 датащи(HTML) 8 Page - Microchip Technology |
8 / 28 page TC500/A/510/514 DS21428B-page 8 © 2002 Microchip Technology Inc. 4.0 TC500/A/510/514 CONVERTER OPERATION The TC500/A/510/514 incorporates an Auto Zero and Integrator phase in addition to the input signal Integrate and reference De-integrate phases. The addition of these phases reduce system errors, calibration steps and shorten overrange recovery time. A typical mea- surement cycle uses all four phases in the following order: 1. Auto Zero 2. Input signal integration 3. Reference deintegration 4. Integrator output zero The internal analog switch status for each of these phases is summarized in Table 4-1. This table references the Typical Application. TABLE 4-1: INTERNAL ANALOG GATE STATUS 4.1 Auto Zero Phase (AZ) During this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging CAZ (auto zero capacitor) with a compensating error voltage. The external input signal is disconnected from the inter- nal circuitry by opening the two SWI switches. The internal input points connect to analog common. The reference capacitor is charged to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capac- itor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages. 4.2 Analog Input Signal Integration Phase (INT) The TC5XX integrates the differential voltage between the (VIN+) and (VIN–) inputs. The differential voltage must be within the device's Common mode range VCMR. The input signal polarity is normally checked via software at the end of this phase: CMPTR = 1 for positive polarity; CMPTR = 0 for negative polarity. 4.3 Reference Voltage De-integration Phase (DINT) The previously charged reference capacitor is con- nected with the proper polarity to ramp the integrator output back to zero. An externally-provided, precision timer is used to measure the duration of this phase. The resulting time measurement is proportional to the magnitude of the applied input voltage. 4.4 Integrator Output Zero Phase (IZ) This phase ensures the integrator output is at 0V when the Auto Zero phase is entered and that only system offset voltages are compensated. This phase is used at the end of the reference voltage de-integration phase and MUST be used for ALL TC5XX applications having resolutions of 12-bits or more. If this phase is not used, the value of the Auto Zero capacitor (CAZ)mustbe about 2 to 3 times the value of the Integration capacitor (CINT) to reduce the effects of charge sharing. The Inte- grator Output Zero phase should be programmed to operate until the output of the comparator returns "HIGH". The overall timing system is shown in Figure 4-1. Conversion Phase SWI SWR+SWR-SWZ SWR SW1 SWIZ Auto Zero (A = 0, B = 1) Closed Closed Closed Input Signal Integration (A = 1, B = 0) Closed Reference Voltage De-integration (A =1, B = 1) Closed* Closed Integrator Output Zero (A = 0, B = 0) Closed Closed Closed Note: *Assumes a positive polarity input signal. SW–RI would be closed for a negative input signal. |
Аналогичный номер детали - TC500 |
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Аналогичное описание - TC500 |
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