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SM3322ARA датащи(PDF) 6 Page - Nippon Precision Circuits Inc |
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SM3322ARA датащи(HTML) 6 Page - Nippon Precision Circuits Inc |
6 / 14 page SM3322ARA SEIKO NPC CORPORATION - 6 AC Characteristics Data Write Mode Recommended operating conditions using reference circuit, unless otherwise noted. Parameter Symbol Conditions MIN TYP MAX Unit Write clock LOW-level pulse width twlw CLK pin 40 - - ns Write clock HIGH-level pulse width twhw CLK pin 40 - - ns Data setup time 1 tsu1 Between SE-CLK 40 - - ns Data setup time 2 tsu2 Between DATA-CLK 40 - - ns Data hold time 1 th1 Between SE-CLK 140 - - ns Data hold time 2 th2 Between DATA-CLK 40 - - ns Write clock frequency fclkw - - 10 MHz Settling time tst OUT pin, 100pF load, 1V output amplitude variation, time to reach 95% level - - 2 μs Output disable time*1 tz OUT pin - 0.1 - μs Input capacitance*2 CI SE,OE,CLK,DATApins - 5 - pF Output capacitance*2 CO OUT pin - 5 - pF Interface wait time tsi 100 - - ns *1. Design value: Provided as a measure for the output control time. *2. Design value: Indicates the terminal capacitance per pin. Provided as a guide for when designing the circuit board. LOW/HIGH-level switch timing measured with respect to 0.5VDD reference level, unless otherwise noted. Data Read Mode Recommended operating conditions using reference circuit, unless otherwise noted. Parameter Symbol Conditions MIN TYP MAX Unit Read clock LOW-level pulse width twlr CLK pin 500 - - ns Read Clock HIGH-level pulse width twhr CLK pin 500 - - ns Read Clock frequency fclkr - - 1 MHz SE hold time tse Between SE-CLK 500 - - ns Read-out data delay time tRD DATApin, 100pF load - - 400 ns LOW/HIGH-level switch timing measured with respect to 0.5VDD reference level, unless otherwise noted. OE SE DATA CLK twlw twhw tsu1 tsu2 th1 th2 1/fclkw tz tst OUT 95% 100% R/W A2 12 3 15 16 A1 GS1 GS0 tsi SE DATA CLK twlr twhr 1/fclkr A2 R/W A1 12 3 8 915 16 tRD 7 GS0 GS1 CS1 CS0 - - tse OE "L" or open tZZ |
Аналогичный номер детали - SM3322ARA |
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Аналогичное описание - SM3322ARA |
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