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SM5165 датащи(PDF) 8 Page - Nippon Precision Circuits Inc |
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SM5165 датащи(HTML) 8 Page - Nippon Precision Circuits Inc |
8 / 10 page SM5165AV NIPPON PRECISION CIRCUITS—8 Operating principles When the PLL is operating with a phase error within fixed tolerance, an internal WINDOWN signal is generated. This signal is in sync with the N counter output signal (FV) and is 62 cycles of the FIN input period in length centered about the falling edge of FV. If the phase detector error correction signal occurs before the WINDOWN LOW-level pulse, the HIGH- level output from DB continues. However, if the error correction signal occurs wholly within the WINDOWN LOW-level pulsewidth, DB goes high impedance and the boost-up circuit operation stops. The above description applies when the error correc- tion signal is revising up. When the error correction signal is revising down, DB goes LOW. Standby Mode The SM5165AV enters standby mode when OPR goes LOW. In this mode, the following pin states and functions occur. Note that even in standby mode, some current flows into VDD1 (FIN and XIN prescaler current). It is recommended that VDD1 be grounded in standby mode to reduce current consumption if necessary. Note also that the above pin states and functions are only valid if VDD2 and VDD3 are maintained within normal operating conditions. If VDD2 and/or VDD3 Function State Outputs DO and DB Floating (high impedance) Phase detector Reset Input FIN Feedback resistor is cutoff (internal HIGH level) Input XIN Feedback resistor is cutoff (internal HIGH level) N counter Reset R counter Reset Latch data Stored are not within normal operating conditions, the latch data is not retained. Phase Comparator Timing Diagram Passive Low-pass Filter FV and FR are the internal comparator frequency divider output signal and reference frequency divider output signal, respectively. FR FV DO LD DO C R2 R1 VCO |
Аналогичный номер детали - SM5165 |
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Аналогичное описание - SM5165 |
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