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DM2502CJ датащи(PDF) 3 Page - National Semiconductor (TI) |
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DM2502CJ датащи(HTML) 3 Page - National Semiconductor (TI) |
3 / 8 page Application Information OPERATION The registers consist of a set of master latches that act as the control elements in the device and change state on the input clock high-to-low transition and a set of slave latches that hold the register data and change on the input clock low-to-high transition Externally the device acts as a special purpose serial-to-parallel converter that accepts data at the D input of the register and sends the data to the appropriate slave latch to appear at the register output and the DO out- put on the DM2502 and DM2504 when the clock goes from low-to-high There are no restrictions on the data input it can change state at any time except during a short interval centered about the clock low-to-high transition At the same time that data enters the register bit the next less significant bit register is set to a low ready for the next iteration The register is reset by holding the S (Start) signal low dur- ing the clock low-to-high transition The register synchro- nously resets to the state Q7 (11) low and all the remaining register outputs high The QCC (Conversion Complete) sig- nal is also set high at this time The S signal should not be brought back high until after the clock low-to-high transition in order to guarantee correct resetting After the clock has gone high resetting the register the S signal must be re- moved On the next clock low-to-high transition the data on the D input is set into the Q7 (11) register bit and the Q6 (10) register bit is set to a low ready for the next clock cycle On the next clock low-to-high transition data enters the Q6 (10) register bit and Q5 (9) is set to a low This operation is repeated for each register bit in turn until the register has been filled When the data goes into Q0 the QCC signal goes low and the register is inhibited from further change until reset by a Start signal The DM2502 DM2503 and DM2504 have a specially tai- lored two-phase clock generator to provide nonoverlapping two-phase clock pulses (ie the clock waveforms intersect below the thresholds of the gates they drive) Thus even at very slow dVdt rates at the clock input (such as from rela- tively weak comparator outputs) improper logic operation will not result LOGIC CODES All three registers can be operated with various logic codes Two’s complement code is used by offsetting the compara- tor full range a LSB and using the complement of the MSB (Q7 or Q11) with a binary DA converter Offset binary is used in the same manner but with the MSB (Q7orQ11) BCD DA converters can be used with the addition of illegal code suppression logic ACTIVE HIGH OR ACTIVE LOW LOGIC The register can be used with either DA converters that require a low voltage level to turn on or DA converters that require a high voltage level to turn the switch on If DA converters are used which turn on with a low logic level the resulting digital output from the register is active low That is a logic ‘‘1’’ is represented as a low voltage level If DA converters are used that turn on with a high logic level then the digital output is active high a logic ‘‘1’’ is represented as a high voltage level EXPANDED OPERATION An active low enable input E on the DM2503 and DM2504 allows registers to be connected together to form a longer register by connecting the clock D and S inputs in parallel and connecting the QCC output of one register to the E input of the next less significant register When the start resets the register the E signal goes high forcing the Q7 (11) bit high and inhibiting the register from accepting data until the previous register is full and its QCC goes low If only one register is used the E input should be held at a low logic level Timing Diagram DM2502 DM2503 TLF5702 – 2 3 |
Аналогичный номер детали - DM2502CJ |
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Аналогичное описание - DM2502CJ |
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