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DM2502CJ датащи(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали DM2502CJ
подробное описание детали  Successive Approximation Registers
Download  8 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

DM2502CJ датащи(HTML) 4 Page - National Semiconductor (TI)

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Application Information (Continued)
SHORT CYCLE
If all bits are not required the register may be truncated and
conversion time saved by using a register output going low
rather then the QCC signal to indicate the end of conversion
If the register is truncated and operated in the continuous
conversion mode a lock-up condition may occur on power
turn-on This condition can be avoided by making the start
input the OR function of QCC and the appropriate register
output
COMPARATOR BIAS
To minimize the digital error below g
LSB the compara-
tor must be biased If a DA converter is used which re-
quires a low voltage level to turn on the comparator should
be biased a
LSB If the DA converter requires a high
logic level to turn on the comparator must be biased b
LSB
Definition of Terms
CP
The clock input of the register
D
The serial data input of the register
DO
The serial data out (The D input delayed one bit)
E
The register enable This input is used to expand the
length of the register and when high forces the Q7 (11)
register output high and inhibits conversion When not used
for expansion the enable is held at a low logic level
(ground)
Qi ie7 (11) to 0 The outputs of the register
QCC The conversion complete output This output remains
high during a conversion and goes low when a conversion is
complete
Q7 (11)
The true output of the MSB of the register
Q7 (11)
The complement output of the MSB of the register
S
The start input If the start input is held low for at least a
clock period the register will be reset to Q7 (11) low and all
the remaining outputs high A start pulse that is low for a
shorter period of time can be used if it meets the set-up time
requirements of the S input
Truth Table
DM2502 DM2503
Time
Inputs
Outputs1
tn
DS
E2
D03
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
QCC
0
X
L
L
X
X
XXXXXXX
X
1
D7
H
L
X
L
HHHHHHH
H
2
D6
H
L
D7
D7
L
HHHHHH
H
3
D5
H
L
D6
D7
D6
L
HHHHH
H
4
D4
H
L
D5
D7
D6
D5
L
HHHH
H
5
D3
H
L
D4
D7
D6D5D4
L
H
H
H
H
6
D2
H
L
D3
D7
D6D5D4D3
L
H
H
H
7
D1
H
L
D2
D7
D6D5D4D3D2
L
H
H
8
D0
H
L
D1
D7
D6D5D4D3D2D1
L
H
9
X
H
L
D0
D7
D6
D5
D4
D3
D2
D1
D0
L
10
X
X
L
X
D7
D6
D5
D4
D3
D2
D1
D0
L
X
X
H
X
H
NCNCNCNCNCNCNC
NC
H
e
High Voltage Level
Note 1
Truth table for DM2504 is extended to include 12 outputs
L
e
Low Voltage Level
Note 2
Truth table for DM2502 does not include E column or last line in truth table shown
X
e
Don’t Care
Note 3
Truth table for DM2503 does not include D0 column
NC e No Change
Typical Applications
BCD Illegal Code Suppression
Active High
Active Low
TLF5702 – 3
4


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