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SM8222A датащи(PDF) 3 Page - Nippon Precision Circuits Inc |
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SM8222A датащи(HTML) 3 Page - Nippon Precision Circuits Inc |
3 / 15 page SM8222A/B NIPPON PRECISION CIRCUITS—3 PIN DESCRIPTION Number Name I/O Description 1 TIP I Tip input: Connected to the telephone through a protection circuit. 2 RING I Ring input: Connected to the telephone through a protection circuit. 3 GS O Input stage amplifier output: Used to select the input amplifier gain 4 AGND O Analog ground: Internal reference voltage (VDD/2) output. 5 CAP I Reference voltage capacitor connection. C = 0.1 µF 6 RDIN I Ring detect input: Line reversal and ring signal detect input. Connect to detect attenuated ring signals. Schmitt-trigger input. 7 RDRC I/O Ring detect RC connection: RC network connection to set the ring detect delay time. Open-drain output and schmitt-trigger input. 8 RDET O Ring detect output: RDRC schmitt-trigger buffer output. LOW when a ring signal is detected. 9 MODE I FSK interface mode select: Demodulated FSK signal output method select. LOW [Mode = 0]: Demodulated data output and data sync clock output. HIGH [Mode = 1]: Data output in sync with an external clock. 10 OSCIN I Crystal oscillator element input: Oscillator element connection between OSCIN and OSCOUT. 11 OSCOUT O Crystal oscillator element output: Oscillator element connection between OSCIN and OSCOUT. 12 GND – Ground: Connect to system ground. 13 IC I Test input: Tie LOW for normal operation. 14 PDWN I Power-down control: LOW for normal operation. HIGH for device power-down state.When device is powered-down, AGND, OSCOUT, DCLK, DOUT, INT, CDET are all HIGH. DR also goes HIGH in mode 0 output. Schmitt-trigger input. 15 FSKEN I FSK signal output control: Demodulated FSK signal output and carrier detect output control. Mode 0: DCLK, DOUT, DR, CDET control Mode 1: DCLK, DOUT, CDET control FSK signal reception enabled when HIGH. Signal pins (above) go HIGH when FSKEN is LOW. 16 DCLK I/O FSK interface clock: Demodulated FSK signal output clock. Mode 0: Clock output in sync with data Mode 1: Data read clock input 17 DOUT O Data output: Demodulated FSK signal output. HIGH-level output when PDWN is HIGH or FSKEN is LOW, or when CDET is HIGH in receive state. 18 DR O Data output trigger: Demodulated FSK data timing output. Active-LOW. Becomes active when 8 bits of data are completed. 19 CDET O Carrier (FSK signal) detect output: Goes LOW when a valid carrier signal is detected. 20 INT O Interrupt signal output: Goes LOW when either RDET is LOW, DR is LOW or STD is HIGH. 21 STD O Dual tone indicator output: Goes HIGH if the dual tone detect signal is recognized after the external RC circuit time delay has elapsed. 22 EST O Dual tone detect output: Goes HIGH when the dual tone is detected. 23 STGT I/O Dual tone RC time constant circuit connection: External RC network connection for dual tone signal detection processing. Sets STD output. 24 VDD – Supply voltage |
Аналогичный номер детали - SM8222A |
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Аналогичное описание - SM8222A |
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