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SI5351B-B-GM датащи(PDF) 10 Page - Silicon Laboratories |
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SI5351B-B-GM датащи(HTML) 10 Page - Silicon Laboratories |
10 / 31 page Si5350C-B 10 Rev. 1.0 3. Functional Description The architecture of the Si5350C generates up to eight non-integer-related frequencies in any combination of free- running and/or synchronous clocks. A block diagram of both the 3-output and the 8-output versions are shown in Figure 4. Free-running clocks are generated using the on-chip oscillator + PLL, and the clock input pin (CLKIN) provides an external input reference for the synchronous clocks. Each MultiSynthTM is configurable with two frequencies (F1_x, F2_x). This allows a pin controlled glitchless frequency change at each output (CLK0 to CLK5). Figure 4. Block Diagrams of the Si5350C Devices with 3 and 8 outputs 10-MSOP MultiSynth 3 F1_2 F2_2 R2 FS MultiSynth 2 VDD GND CLK2 F1_0 F2_0 R0 FS MultiSynth 0 F1_1 F2_1 R1 FS MultiSynth 1 CLK0 CLK1 VDDO F1_3 F2_3 R3 FS MultiSynth 3 F1_2 F2_2 R2 FS MultiSynth 2 20-QFN VDD GND CLK2 CLK3 VDDOB Control Logic P2 P3 P0 P1 F1_0 F2_0 R0 FS MultiSynth 0 F1_1 F2_1 R1 FS MultiSynth 1 CLK0 CLK1 VDDOA R6 R7 CLK6 CLK7 VDDOD F1_4 F2_4 R4 FS MultiSynth 4 F1_5 F2_5 R5 FS MultiSynth 5 CLK4 CLK5 VDDOC F1_6 MultiSynth 6 F1_7 MultiSynth 7 Control Logic P0 PLL A OSC XA XB CLKIN PLL A OSC XA XB CLKIN PLL B PLL B |
Аналогичный номер детали - SI5351B-B-GM |
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Аналогичное описание - SI5351B-B-GM |
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