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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD5761RBCPZ-RL7 датащи(PDF) 7 Page - Analog Devices |
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AD5761RBCPZ-RL7 датащи(HTML) 7 Page - Analog Devices |
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7 / 35 page  Data Sheet AD5761R/AD5721R TIMING CHARACTERISTICS DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Description t11 20 ns min SCLK cycle time t2 10 ns min SCLK high time t3 10 ns min SCLK low time t4 15 ns min SYNC falling edge to SCLK falling edge setup time t5 10 ns min SCLK falling edge to SYNC rising edge time t6 20 ns min Minimum SYNC high time (write mode) t7 5 ns min Data setup time t8 5 ns min Data hold time t9 10 ns min LDAC falling edge to SYNC falling edge t10 20 ns min SYNC rising edge to LDAC falling edge t11 20 ns min LDAC pulse width low t12 9 µs typ DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 2) 7.5 µs typ DAC output settling time, 10 V step to 1 LSB at 16-bit resolution t13 20 ns min CLEAR pulse width low t14 200 ns typ CLEAR pulse activation time t15 10 ns min SYNC rising edge to SCLK falling edge t16 40 ns max SCLK rising edge to SDO valid (CL_SDO2 = 15 pF) t17 50 ns min Minimum SYNC high time (readback/daisy-chain mode) 1 Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode. 2 CL_SDO is the capacitive load on the SDO output. TIMING DIAGRAMS DB23 SCLK SYNC SDI LDAC CLEAR VOUT VOUT VOUT 4 2 2 1 DB0 t12 t12 t10 t11 t14 t13 t9 t8 t7 t4 t6 t3 t2 t1 t5 Figure 2. Serial Interface Timing Diagram Rev. A | Page 7 of 35 |
Аналогичный номер детали - AD5761RBCPZ-RL7 |
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Аналогичное описание - AD5761RBCPZ-RL7 |
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