Si53159

Rev. 1.1

5

Table 2. AC Electrical Specifications

Parameter

Symbol

Condition

Min

Typ

Max

Unit

DIFFIN at 0.7 V

DIFFIN and DIFFIN

Rising/Falling Slew Rate

Single ended measurement:

(Averaged)

0.6

—

4

V/ns

Differential Input High Voltage

150

—

—

mV

Differential Input Low Voltage

—

—

–150

mV

Crossing Point Voltage at 0.7 V

Swing

Single-ended measurement

250

—

550

mV

Vcross Variation Over All edges



Single-ended measurement

—

—

140

mV

Differential Ringback Voltage

–100

—

100

mV

Time before Ringback Allowed

500

—

—

ps

Absolute Maximum Input Voltage

—1.15

V

Absolute Minimum Input Voltage

–0.3

—

—

V

DIFFIN and DIFFIN Duty Cycle

45

—

55

%

Rise/Fall Matching

Determined as a fraction of

——

20

%

DIFF at 0.7 V

Duty Cycle

Measured at 0 V differential

45

—

55

%

Clock Skew

Measured at 0 V differential

—

—

50

ps

PCIe Gen1 Pk-Pk Jitter

Pk-Pk

PCIe Gen 1

0

—

10

ps

PCIe Gen 2 Phase Jitter

10 kHz < F < 1.5 MHz

0

—

0.5

ps

1.5 MHz < F < Nyquist

0

—

0.5

ps

PCIe Gen 3 Phase Jitter

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

0

—

0.10

ps

PCIe Gen 4

—

—

0.10

ps

Additive Cycle to Cycle Jitter

In buffer mode.

Measured at 0 V differential

—20

50

ps

Long-term Accuracy

Measured at 0 V differential

—

—

100

ppm

Rising/Falling Slew rate

Measured differentially from

±150 mV

2.5

—

8

V/ns

Crossing Point Voltage at 0.7 V

Swing

300

—

550

mV

Notes:

2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.

3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.