CDCE913PWG4 datasheet(6/35 Pages) TI1

номер детали	CDCE913PWG4

подробное описание детали	Programmable 1-PLL VCXO Clock Synthesizer

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CDCE913, CDCEL913

SCAS849F – JUNE 2007 – REVISED APRIL 2015

www.ti.com

Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

tPLH, tPHL

Propagation delay

PLL bypass

3.2

ns

tr/tf

Rise and fall time

VDDOUT = 3.3 V (20%–80%)

0.6

ns

tjit(cc)

Cycle-to-cycle jitter(2)(3)

1 PLL switching, Y2-to-Y3

50

70

ps

tjit(per)

Peak-to-peak period jitter(3)

1 PLL switching, Y2-to-Y3

60

100

ps

tsk(o)

Output skew (4), See Table 2

fOUT = 50 MHz; Y1-to-Y3

60

ps

odc

Output duty cycle (5)

fVCO = 100 MHz; Pdiv = 1

45%

55%

CDCE913 – LVCMOS PARAMETER for VDDOUT = 2.5 V – MODE

VDDOUT = 2.3 V, IOH = –0.1 mA

2.2

VOH

LVCMOS high-level output voltage

VDDOUT = 2.3 V, IOH = –6 mA

1.7

V

VDDOUT = 2.3 V, IOH = –10 mA

1.6

VDDOUT = 2.3 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

VDDOUT = 2.3 V, IOL = 6 mA

0.5

V

VDDOUT = 2.3 V, IOL = 10 mA

0.7

tPLH, tPHL

Propagation delay

PLL bypass

3.6

ns

tr/tf

Rise and fall time

VDDOUT = 2.5 V (20%–80%)

0.8

ns

tjit(cc)

Cycle-to-cycle jitter(2)(3)

1 PLL switching, Y2-to-Y3

50

70

ps

tjit(per)

Peak-to-peak period jitter(3)

1 PLL switching, Y2-to-Y3

60

100

ps

tsk(o)

Output skew(4) , See Table 2

fOUT = 50 MHz; Y1-to-Y3

60

ps

odc

Output duty cycle(5)

fVCO = 100 MHz; Pdiv = 1

45%

55%

CDCEL913 — LVCMOS PARAMETER for VDDOUT = 1.8 V – MODE

VDDOUT = 1.7 V, IOH = –0.1 mA

1.6

VOH

LVCMOS high-level output voltage

VDDOUT = 1.7 V, IOH = –4 mA

1.4

V

VDDOUT = 1.7 V, IOH = –8 mA

1.1

VDDOUT = 1.7 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

VDDOUT = 1.7 V, IOL = 4 mA

0.3

V

VDDOUT = 1.7 V, IOL = 8 mA

0.6

tPLH, tPHL

Propagation delay

PLL bypass

2.6

ns

tr/tf

Rise and fall time

VDDOUT = 1.8 V (20%–80%)

0.7

ns

tjit(cc)

Cycle-to-cycle jitter(2)(3)

1 PLL switching, Y2-to-Y3

80

110

ps

tjit(per)

Peak-to-peak period jitter(3)

1 PLL switching, Y2-to-Y3

100

130

ps

tsk(o)

Output skew(4), See Table 2

fOUT = 50 MHz; Y1-to-Y3

50

ps

odc

Output duty cycle(5)

fVCO = 100 MHz; Pdiv = 1

45%

55%

SDA/SCL PARAMETER

VIK

SCL and SDA input clamp voltage

VDD = 1.7 V; II = –18 mA

–1.2

V

IIH

SCL and SDA input current

VI = VDD; VDD = 1.9 V

±10

μA

VIH

SDA/SCL input high voltage(6)

0.7 VDD

V

VIL

SDA/SCL input low voltage(6)

0.3 VDD

V

VOL

SDA low-level output voltage

IOL = 3 mA, VDD = 1.7 V

0.2 VDD

V

CI

SCL/SDA input capacitance

VI = 0 V or VDD

3

10

pF

(2)

10,000 cycles.

(3)

Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).

(4)

The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.

(5)

odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr)

(6)

SDA and SCL pins are 3.3-V tolerant.

6.6 EEPROM Specification

MIN

TYP

MAX

UNIT

EEcyc

Programming cycles of EEPROM

100

1000

cycles

EEret

Data retention

10

years

6

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Product Folder Links: CDCE913 CDCEL913

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