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SI4742 датащи(PDF) 9 Page - Silicon Laboratories |
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SI4742 датащи(HTML) 9 Page - Silicon Laboratories |
9 / 20 page AN400 Rev. 0.5 9 2.5. Si474x 4x4 mm Design Checklist The following design checklist summarizes the guidelines presented in this section: Place bypass caps C1, C6, and C18 (for VDD) and C13, C17, and C19 (for VIO) as close as possible to the supply and ground pins. Place a VIA connecting C1, C6, and C18 (for VDD) and C13, C17, and C19 (for VIO) such that the cap is between the Si47xx and the VIA. Route a wide, low-inductance return current path from the C1, C6, C13, C17, C18, and C19 to the Si47xx GND pins. Place resistor R16 as close to DOUT pin 17 as possible. Place the series termination resistors, R12, R14, R21, R24, R26, R29, and R30 as close to the host controller as possible. Place the pull-up/pull-down resistors, R2, R13, R22, and R23, as close to the DFS (pin 18) and RCLK (pin 11) as possible. Place shunt cap C2 from DFS to gnd and as close to DFS (pin 18) as possible. Place a ground plane under the device as shown in Figure 4, “Two-Layer Stackup”. Place a local ground plane directly under the device for designs in which a continuous ground plane is not possible. Route all traces to minimize inductive and capacitive coupling by keeping digital traces away from analog and RF traces, minimizing trace length, minimizing parallel trace runs, and keeping current loops small. Route digital traces on the opposite side of the chip. Place stitching VIAs around digital traces to minimize current loop areas. Route digital traces RSTb, SENb, SCLK, SDIO, RCLK, DOUT, DFS, and DCLK away from and orthogonal to RF traces to minimize digital noise coupling onto RF traces. Choose DCLK and RCLK frequencies that fall above the AM band. Ensure that timing requirements are met for both RCLK and DCLK with higher frequencies. Refer to “AN332: Si47xx Programming Guide” for timing requirements. Route all GND (including RFGND) pins to the ground pad. The ground pad should be connected to the ground plane using multiple VIAs to minimize ground potential differences. Route power to the Si474x by trace, ensuring that each trace is rated to handle the required current. Do not route signal traces on the ground layer directly under the Si474x. Do not route signal traces under the Si474x without a ground plane between the Si474x and signal trace. Do not route digital or RF traces over breaks in the ground plane. If the design is flexible to have more than two layers, put the GND plane between RF signals and digital signals. Another improvement would be to put the digital signals between two GND planes. Do not route digital signals or reference clock traces near VCO pins 22 and 23 or LOUT/ROUT output pins 15 and 16. Do not route VCO pins 22 and 23 (NC). These pins must be left floating to guarantee proper operation. Do not route pin 24 (NC). This pin must be left floating to guarantee proper operation. Do not route pin 4 (NC). This pin must be left floating to guarantee proper operation. Flood the primary and secondary layers with ground and place stitching VIAs. Place the Si474x close to the antenna(s) to minimize antenna trace length and capacitance and inductive and capacitive coupling. This recommendation must be followed for optimal device performance. Route the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive coupling. Design, Place, and Route other circuits such that radiation in the band of interest is minimized. Tie unused pin(s) to GND, but do not tie No Connect (NC) or unused GPO pins to GND. |
Аналогичный номер детали - SI4742 |
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Аналогичное описание - SI4742 |
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