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SI4822 датащи(PDF) 8 Page - Silicon Laboratories

номер детали SI4822
подробное описание детали  Si4822/26/27/40/44 ANTENNA, SCHEMATIC, LAYOUT, AND DESIGN GUIDELINES
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производитель  SILABS [Silicon Laboratories]
домашняя страница  http://www.silabs.com
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AN602
8
Rev. 0.3
3. Si48422/26/27/40/44 SSOP/SOIC Schematic and Layout
This section shows the typical schematic and layout required for optimal Si4822/26/27/40/44 performance. Si4822/
26/40/44 offer two methods to select the radio band by tuner setting and two methods to set band property by tuner
setting. Normally, there are four kinds of typical application circuits in real application, however, the Si4827 offers
two methods to select the radio band by tuner setting and two methods to set band property by host MCU, so there
are two kinds of typical application circuits in real application.
3.1. Si4822/26/40/44 Application Circuit: Host MCU Select Radio Band and Set Band
Property
Figure 4 shows the applications circuits of Si4822/26/40/44 when the application is to use the host MCU to select
radio band and set band property. Normally, a push button for selecting band is connected to the host MCU. The
MCU then detects the push button’s action and sends a command to Si4822/26/40/44 to set the desired band. The
host MCU can also set the band property, such as band top frequency point and bottom frequency point, stereo
indication threshold (only for Si4840/44), de-emphasis, AM tuning spacing, etc. The two key points to ensure
Si4822/26/40/44 works properly are as follows:
1. No pull-up resistor is connected to pin 1 LNA_EN
2. Pin 5 BAND is connected to its power supply VCC directly
C6 & C15 are required bypass capacitors for VDD1/VDD2 power supply pin 20/21. Place C6/C15 as close as
possible to the VDD1/VDD2 pin 20/21 and DBYP pin 22. These recommendations are made to reduce the size of the
current loop created by the bypass cap and routing, minimize bypass cap impedance, and return all currents to the
DBYP pin.
Pin 22 is the dedicated bypass capacitor pin. Do not connect it to power supply GND on PCB.
Pin 13 and pin 14 are the GND of the chip; these pins must be well connected to the power supply GND on PCB.
Pin 9 is the RFGND of the chip; it must be well connected to the power supply GND on PCB.
C4 and/or C7 (4.7 µF) are ac coupling caps for receiver analog audio output from pin 23 and/or pin 24. The input
resistance of the amplifier, R, such as a headphone amplifier, and the capacitance, C, will set the high pass pole
given by Equation 1. Placement locations of C4 and C7 are not critical.
Equation 1. High-Pass Pole Calculation
C28 and C29 (22 pF) are crystal loading caps required only when using the internal oscillator feature. Refer to the
crystal data sheet for the proper load capacitance and be certain to account for parasitic capacitance. Place caps
C28 and C29 such that they share a common GND connection and the current loop area of the crystal and loading
caps is minimized.
Y1 (32.768 kHz) is an optional crystal required only when using the internal oscillator feature. Place the crystal Y1
as close to XTALO pin 18 and XTALI pin 19 as possible to minimize current loops. If applying an external clock
(32.768 kHz) to XTALI, leave XTALO floating.
Do not route digital signals or reference clock traces near pin 6 and 7. Do not route Pin 6 & 7. These pins must be
left floating to guarantee proper operation.
Pin 2, 15, 16, 17 are the required communication pins with host MCU. A 100 k
 pull-up resistor R6 and 0.1 µF
bypass cap C19 are recommended for the pin 15 RST. Pull-up resistor R3 of 10 k
 is necessary for pin 16 SDIO.
VR1 (100 k / 10%), R27, C1, C13 constitute the tuning circuit. 100k
at 10% tolerance is recommended for VR1.
Q1(2SC9018), together with its peripherals B6, C30,31,33,36, R31,32,34,41, is the LNA circuit for all SW bands.
The LNA is switched off by LNA_EN signal in AM and FM mode controlled by Si4826/44.
For Si4822/26, do not route pin 23. This pin must be left floating to guarantee proper operation.
f
c
1
2
RC
----------------
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