поискавой системы для электроныых деталей |
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TPL5100 датащи(PDF) 9 Page - Texas Instruments |
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TPL5100 датащи(HTML) 9 Page - Texas Instruments |
9 / 20 page TCAL DONE MOS_DRV INT. OSC. PGOOD A B C D TPL5100 www.ti.com SNAS629C – JULY 2013 – REVISED DECEMBER 2014 Feature Description (continued) 7.3.2.1 Overview of the Timing Signals MOS_DRV, TCAL, and DONE Figure 6 shows the timing of PGOOD, MOS_DRV, and TCAL with respect to DONE. The frame, A, shows a typical sequence after the PGOOD, low to high, transition. As soon as PGOOD is high, the internal oscillator is powered ON. At the end of the delay period (tDP), a MOS enable signal (MOS_DRV), followed by a calibration pulse, TCAL, is sent out. The calibration pulse starts after a half period of the internal oscillator from the falling edge of the MOS_DRV signal, and lasts one internal oscillator period. A "DONE" signal is received before the end of the MOS_DRV pulse. As soon as the TPL5100 receives the DONE signal, the counter resets and MOS_DRV and TCAL return to default conditions (MOS_DRV signal high and TCAL signal low). The frame, B, shows a non-standard sequence. A "DONE" signal has not been received before the end of the MOS_DRV pulse. The MOS_DRV signal stays low for 2 internal oscillator periods. The calibration pulse starts after a half period of the internal oscillator from the falling edge of the MOS_DRV signal, and lasts one internal oscillator period. The external power gating MOS stays ON for 2 internal oscillator periods. The frame, C, shows a standard sequence, but in this case, the TPL5100 receives the DONE signal when MOS_DRV is high and TCAL pulse is still high. As soon as the TPL5100 recognizes the DONE signal, the counter resets and MOS_DRV and TCAL return to default conditions (MOS_DRV signal high and TCAL signal low).The external power-gating MOS stays ON for the execution time of the program of the connected microcontroller. The frame, D, shows a typical PGOOD, high to low transition. As soon as PGOOD is low, the internal oscillator is powered OFF and the digital output pins, TCAL and MOS_DRV, are asynchronously reset by the falling edge of the PGOOD signal, such that TCAL resets at low logical values, while MOS_DRV resets at a high logical value. The external power gating MOS stays ON less than the execution time of the program of the connected microcontroller. Figure 6. Timing MOS_DRV, TCAL 7.3.3 Configuration and Interface The time interval between 2 adjacent pulses is selectable through 3 digital input pins (D0, D1, D2) that can be strapped to either VDD (1) or GND (0). Eight possible time delays can be selected, as shown in Table 1. Table 1. Timer Delay Period D2 D1 D0 Time (s) Factor N 0 0 0 16 210 0 0 1 32 211 0 1 0 64 212 0 1 1 100 100*26 Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPL5100 |
Аналогичный номер детали - TPL5100 |
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Аналогичное описание - TPL5100 |
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