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DAC7562T датащи(PDF) 9 Page - Texas Instruments |
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DAC7562T датащи(HTML) 9 Page - Texas Instruments |
9 / 60 page SCLK SYNC D IN V x OUT DB23 DB0 LDAC (1) LDAC (2) CLR t (2) t (6) t (9) t (10) t (8) t (5) t (3) t (12) t (13) t (14) t (11) t (1) t (4) t (7) DAC7562T, DAC7563T, DAC8162T DAC8163T, DAC8562T, DAC8563T www.ti.com SLASE61A – SEPTEMBER 2015 – REVISED OCTOBER 2015 7.6 Timing Requirements (1) (2) At AVDD = 2.7 V to 5.5 V, external VREFIN = 2.5 V to 5.5 V, and over –40°C to 125°C (unless otherwise noted). See Figure 1. DAC756xT, DAC816xT, DAC856xT UNIT MIN TYP MAX f(SCLK) Serial clock frequency 50 MHz t(1) SCLK falling edge to SYNC falling edge (for successful write operation) 10 ns t(2) SCLK cycle time 20 ns t(3) SYNC rising edge to 23rd SCLK falling edge (for successful SYNC interrupt) 13 ns t(4) Minimum SYNC HIGH time 15 ns t(5) SYNC to SCLK falling edge setup time 13 ns t(6) SCLK LOW time 8 ns t(7) SCLK HIGH time 8 ns t(8) SCLK falling edge to SYNC rising edge 10 ns t(9) Data setup time 6 ns t(10) Data hold time 6 ns t(11) SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode 5 ns t(12) LDAC pulse duration, LOW time 10 ns t(13) CLR pulse duration, LOW time 80 ns t(14) CLR falling edge to start of VOUT transition 100 ns (1) All input signals are specified with tr = tf = 1 ns/V (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH) / 2. (2) See the Serial Write Operation timing diagram (Figure 1). (1) Asynchronous LDAC update mode. For more information, see the LDAC Functionality section. (2) Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section. Figure 1. Timing Diagram, Serial Write Operation Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DAC7562T DAC7563T DAC8162T DAC8163T DAC8562T DAC8563T |
Аналогичный номер детали - DAC7562T |
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Аналогичное описание - DAC7562T |
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