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SN74GTL2003PWR датащи(PDF) 10 Page - Texas Instruments

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номер детали SN74GTL2003PWR
подробное описание детали  8-Bit Bidirectional Low-Voltage Translator
Download  25 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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SN74GTL2003PWR датащи(HTML) 10 Page - Texas Instruments

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S
REF
D
REF
G
REF
SW
SW
GTL2003
D1
S1
D2
S2
R
R
R
R
R
PU
PU
PU
PU
PU
V
= 3.3V
DPU
V
= 1.8V
REF
R
200K
PU
CPU I/O
Chipset
I/O
Chipset
I/O
S7
D7
D8
S8
GND
V
= 5 V
DPU
SN74GTL2003
SCDS305B – FEBRUARY 2011 – REVISED JUNE 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
SN74GTL2003 is a GTL/GTL+ to LVTTL/TTL bidirectional voltage level translator. This device can be used in
both unidirectional applications and bidirectional. Please find the reference schematics and recommended values
for passive components in the Typical Applications.
9.2 Typical Applications
9.2.1 Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the GREF input must be connected to DREF and both pins pulled to HIGH-side VCC through a pullup resistor
(typically 200 k
Ω). TI recommends a filter capacitor on DREF. The processor output can be totem pole or open
drain (pullup resistors) and the chipset output can be totem pole or open drain (pullup resistors are required to
pull the Dn outputs to VCC). However, if either output is totem pole, data must be unidirectional or the outputs
must be 3-statable, and the outputs must be controlled by some direction-control mechanism to prevent HIGH-to-
LOW contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite
side of the reference transistor (SREF) is connected to the processor core power-supply voltage. When DREF is
connected through a 200-k
Ω resistor to a 3.3-V to 5.5-V VCC supply and SREF is set from 1 V to VCC 1.5 V, the
output of each Sn has a maximum output voltage equal to SREF, and the output of each Dn has a maximum
output voltage equal to VCC.
Figure 6. Bidirectional Translation to Multiple Higher Voltage Levels
(Such as an I2C or SMBus Applications)
10
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Product Folder Links: SN74GTL2003


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