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SM470R1B1MHKPS датащи(PDF) 1 Page - Texas Instruments |
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SM470R1B1MHKPS датащи(HTML) 1 Page - Texas Instruments |
1 / 79 page Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design SM470R1B1M-HT SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015 SM470R1B1M-HT 16-/32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 – Two High-End CAN Controllers (HECC) • High-Performance Static CMOS Technology • 32-Mailbox Capacity • SM470R1x 16-/32-Bit RISC Core ( ARM7TDMI™) • Fully Compliant With CAN Protocol, Version – 60-MHz System Clock (Pipeline Mode) 2.0B – Independent 16-/32-Bit Instruction Set – Five Inter-Integrated Circuit (I2C) Modules – Open Architecture With Third-Party Support • Multi-Master and Slave Interfaces – Built-In Debug Module • Up to 400 Kbps (Fast Mode) • Integrated Memory • 7- and 10-Bit Address Capability – 1MB Program Flash • High-End Timer Lite (HET) • Two Banks With 16 Contiguous Sectors – 12 Programmable I/O Channels: – 64KB Static RAM (SRAM) • 12 High-Resolution Pins – Memory Security Module (MSM) – High-Resolution Share Feature (XOR) – JTAG Security Module – High-End Timer RAM • Operating Features • 64-Instruction Capacity – Low-Power Modes: STANDBY and HALT • External Clock Prescale (ECP) Module – Industrial Temperature Range – Programmable Low-Frequency External Clock • 470+ System Module (CLK) – 32-Bit Address Space Decoding • 12-Channel, 10-Bit Multi-Buffered ADC (MibADC) – Bus Supervision for Memory/Peripherals – 64-Word FIFO Buffer – Digital Watchdog (DWD) Timer – Single- or Continuous-Conversion Modes – Analog Watchdog (AWD) Timer – 1.55-µs Minimum Sample and Conversion Time – Enhanced Real-Time Interrupt (RTI) – Calibration Mode and Self-Test Features – Interrupt Expansion Module (IEM) • Flexible Interrupt Handling – System Integrity and Failure Detection • Expansion Bus Module (EBM) – ICE Breaker – Supports 8- and 16-Bit Expansion Bus Memory • Direct Memory Access (DMA) Controller Interface Mappings – 32 Control Packets and 16 Channels – 42 I/O Expansion Bus Pins • Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock • 46 Dedicated General-Purpose I/O (GIO) Pins and Module With Prescaler 47 Additional Peripheral I/Os – Multiply-by-4 or -8 Internal ZPLL Option • Sixteen External Interrupts – ZPLL Bypass Mode • On-Chip Scan-Base Emulation Logic, IEEE • Twelve Communication Interfaces: Standard 1149.1 (1) (JTAG) Test-Access Port – Two Serial Peripheral Interfaces (SPIs) • Available in KGD, HFQ, HKP, and PGE Packages – 255 Programmable Baud Rates (1) The test-access port is compatible with the IEEE Standard – Three Serial Communication Interfaces (SCIs) 1149.1-1990, IEEE Standard Test-Access Port and Boundary • 224 Selectable Baud Rates Scan Architecture specification. Boundary scan is not • Asynchronous/Isosynchronous Modes supported on this device. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
Аналогичный номер детали - SM470R1B1MHKPS |
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Аналогичное описание - SM470R1B1MHKPS |
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