B2

B3

A2

A3

A1

GND

B1

GATE

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SN74TVC3306

SCDS112D – MARCH 2001 – REVISED DECEMBER 2014

SN74TVC3306 Dual Voltage Clamp

1 Features

3 Description

The SN74TVC3306 device provides three parallel

1

•

Designed to Be Used in Voltage-Limiting

NMOS pass transistors with a common unbuffered

Applications

gate. The low on-state resistance of the switch allows

•

3.5-

Ω On-State Connection Between

connections to be made with minimal propagation

Ports A and B

delay.

•

Flow-Through Pinout for Ease of Printed Circuit

The device can be used as a dual switch, with the

Board Trace Routing

gates cascaded together to a reference transistor.

•

Direct Interface With GTL+ Levels

The low-voltage side of each pass transistor is limited

to a voltage set by the reference transistor. This is

•

Latch-Up Performance Exceeds 100 mA Per

done to protect components with inputs that are

JESD 78, Class II

sensitive to high-state voltage-level overshoots.

•

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model

Device Information(1)

–

200-V Machine Model

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SM8 (8)

3.00 mm x 2.80 mm

–

1000-V Charged-Device Model

SN74TVC3306

US8 (8)

2.30 mm x 2.00 mm

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Voltage Level Translation

•

Signal Switching

•

Bus Isolation

4 Simplified Schematic

The SN74TVC3306 device has bidirectional capability across many voltage levels. The voltage levels documented in

this data sheet are examples.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.