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ADC0833BCN датащи(PDF) 5 Page - National Semiconductor (TI) |
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ADC0833BCN датащи(HTML) 5 Page - National Semiconductor (TI) |
5 / 20 page AC Electrical Characteristics The following specifications apply for VCC e Va e 5V and tr e tf e 20 ns unless otherwise specified These limits apply for TA e Tj e 25 C Typ Tested Design Parameter Conditions (Note 6) Limit Limit Units (Note 7) (Note 8) fCLK Clock Frequency Min 10 kHz Max 400 kHz TC Conversion Time Not including MUX Addressing Time 8 1fCLK Clock Duty Cycle (Note 12) Min 40 % Max 60 % tSET-UP CS Falling Edge or 250 ns Data Input Valid to CLK Rising Edge tHOLD Data Input Valid 90 ns after CLK Rising Edge tpd1 tpd0 CLK Falling CL e 100 pF Edge to Output Data Valid Data MSB First 650 1500 ns (Note 13) Data LSB First 250 600 ns t1H tOH Rising Edge of CS CL e 10 pF RL e 10k 125 250 ns to Data Output and SARS CL e 100 pF RL e 2k 500 ns Hi-Z (see TRI-STATE Test Circuits) CIN Capacitance of Logic 5 pF Input COUT Capacitance of Logic 5 pF Outputs Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to the ground pins Note 3 Internal zener diodes (approx 7V) are connected from Va to GND and VCC to GND The zener at Va can operate as a shunt regulator and is connected to VCC via a conventional diode Since the zener voltage equals the AD’s breakdown voltage the diode insures that VCC will be below breakdown when the device is powered from Va Functionality is therefore guaranteed for Va operation even though the resultant voltage at VCC may exceed the specified Absolute Max of 65V It is recommended that a resistor be used to limit the max current into Va Note 4 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l Va) the absolute value of current at that pin should be limited to 5 mA or less The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mA current limit to four Note 5 Human body model 100 pF discharged through a 15 kX resistor Note 6 Typicals are at 25 C and represent most likely parametric norm Note 7 Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) Note 8 Design limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels Note 9 See Applications section 30 Note 10 For VIN(b)tVIN(a) the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply Be careful during testing at low VCC levels (45V) as high level analog inputs (5V) can cause this input diode to conductespecially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC to5VDC input voltage range will therefore require a minimum supply voltage of 4950 VDC over temperature variations initial tolerance and loading Note 11 Leakage current is measured with the clock not switching Note 12 A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or the minimum time the clock is low must be at least 1ms The maximum time the clock can be high is 60 ms The clocked can be stopped when low so long as the analog input voltage remains stable Note 13 Since data MSB first is the output of the comparator used in the successive approximation loop an additional delay is built in (see Block Diagram) to allow for comparator response time 5 |
Аналогичный номер детали - ADC0833BCN |
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Аналогичное описание - ADC0833BCN |
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