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ADC08351 датащи(PDF) 9 Page - National Semiconductor (TI) |
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ADC08351 датащи(HTML) 9 Page - National Semiconductor (TI) |
9 / 15 page Timing Diagram (Continued) Functional Description The ADC08351 achieves 6.8 effective bits at 21 MHz input frequency with 42 MHz clock frequency digitizing to eight bits the analog signal at V IN that is within the nominal voltage range of 0.5 V P-P to 0.68 VA. Input voltages below 0.0665 times the reference voltage will cause the output word to consist of all zeroes, while input voltages above 3⁄4 of the reference voltage will cause the out- put word to consist of all ones. For example, with a V REF of 2.4V, input voltages below 160 mV will result in an output word of all zeroes, while input voltages above 1.79V will re- sult in an output word of all ones. The output word rate is the same as the clock frequency. Data is acquired at the falling edge of the clock and the digi- tal equivalent of that data is available at the digital outputs 2.5 clock cycles plus t OD later. The ADC08351 will convert as long as the clock signal is present at pin 12, but the data will not appear at the outputs unless the OE pin 1 is low. The digital outputs are in the high impedance state when the OE pin or when the PD pin is high. Applications Information 1.0 THE ADC REFERENCE AND THE ANALOG INPUT The capacitance seen at the input changes with the clock level, appearing as 4 pF when the clock is low, and 11 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than is a fixed capacitance, choose an ampli- fier that can drive this type of load. The CLC409, CLC440, LM6152, LM6154, LM6181 and LM6182 are good devices for driving analog input of the ADC08351. Do not drive the in- put beyond the supply rails. The maximum peak-to-peak input level without clipping of the reconstructed output is determined by the values of the resistor string between V REF and AGND. The bottom of the reference ladder has a voltage of 0.0665 times V REF, while the top of the reference ladder has a voltage of 0.7468 times V REF. The maximum peak-to-peak input level works out to be about 68% of the value of V REF. The relationship between the input peak-to-peak voltage and V REF is We do not recommend opertaing with input levels below 1V P-P because the signal-to-noise ratio will degrade consid- erably due to the quantization noise. However, the ADC08351 will give adequate results in many applications with signal levels down to about 0.5 V P-P (VREF = 0.735V). Very good performance can be obtained with reference volt- ages up to the supply voltage (V A =VREF = 3V, 2.04 VP-P). As with all sampling ADCs, the opening and closing of the switches associated with the sampling causes an output of energy from the analog input, V IN. The reference ladder also has switches associated with it, so the reference source must be able to supply sufficient current to hold V REF steady. The analog input of the ADC08351 is self-biased with an 18 k Ω pull-up resistor to V REF anda12kΩ pull-down resistor to AGND. This allows for either a.c. or d.c. coupling of the in- put signal. These two resistors provide a convenient way to ensure a signal that is less than full scale will be centered within the input common mode range of the converter. How- ever, the high values of these resistors and the energy com- ing from this input means that performance will be improved with d.c. coupling. The driving circuit at the signal input must be able to sink and source sufficient current at the signal frequency to prevent distortion from being introduced at the input. 2.0 POWER SUPPLY CONSIDERATIONS A tantalum or aluminum electrolytic capacitor of 5 µF to 10 µF should be placed within a centimeter of each of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed within 1⁄2 centimeter of each of the power pins. Leadless chip capacitors are preferred because they provide lower lead in- ductance than do their leaded counterparts. While a single voltage source should be used for the analog and digital supplies of the ADC08351, these supply pins should be decoupled from each other to prevent any digital noise from being coupled to the analog power pins. A ferrite bead between the analog and digital supply pins would help to isolate the two supplies. The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should be the same supply used for the A/D analog supply, decoupled from the A/D analog supply pin, as described above. A common analog supply should be used for both V A and VD, and each of these pins should be separately bypassed with a 0.1 µF ceramic capacitor and with low ESR a 10 µF capacitor. As is the case with all high speed converters, the ADC08351 is sensitive to power supply noise. Accordingly, the noise on DS100895-24 FIGURE 2. t EN,tDIS Test Circuit www.national.com 9 |
Аналогичный номер детали - ADC08351 |
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Аналогичное описание - ADC08351 |
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