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AD7779 датащи(PDF) 10 Page - Analog Devices

номер детали AD7779
подробное описание детали  8-Channel, 24-Bit, Simultaneous Sampling ADC
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD7779 датащи(HTML) 10 Page - Analog Devices

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AD7779
Data Sheet
Rev. 0 | Page 10 of 97
SPI TIMING CHARACTERISTISTICS
AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− =
2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Description1
Test Conditions/Comments
Min
Typ
Max
Unit
t12
SCLK Period
50:50
30
MHz
t13
SCLK Low Time
7
ns
t14
SCLK High Time
7
ns
t15
SCLK Rising Edge to CS Falling Edge
10
ns
t16
CS Falling Edge to SCLK Rising Edge
10
ns
t17
SCLK Rising Edge to CS Rising Edge
10
ns
t18
CS Rising Edge to SCLK Rising Edge
10
ns
t19
Minimum CS High Time
10
ns
t20
SDI Setup Time
5
ns
t21
SDI Hold Time
5
ns
t22A
CS Falling Edge to SDO Enable (SPI = Mode 0)
30
ns
t22B
SCLK Falling Edge to SDO Enable (SPI = Mode 1)
49
ns
t23
SDO Setup Time
10
ns
t24
SDO Hold Time
10
ns
t25
CS Rising Edge to SDO Disable
30
ns
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
CS
SCLK
MSB
MSB – 1
LSB + 1
LSB
SDI
MSB
MSB – 1
LSB + 1
LSB
SDO
t15
t16
t13
t14
t20
t22A
t21
t24
t23
t22B
t12
t19
t17
t18
t25
Figure 3. SPI Control Interface Timing Diagram


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