поискавой системы для электроныых деталей |
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AD9262-10EBZ датащи(PDF) 9 Page - Analog Devices |
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AD9262-10EBZ датащи(HTML) 9 Page - Analog Devices |
9 / 32 page AD9262 Rev. A | Page 9 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPACITY OF THE PACKAGE. PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK– CVDD D0B D1B D2B DVDD DGND DRVDD D3B D4B D5B D6B D7B D8B D9B D10B SCLK SDIO ORA D15A D14A DVDD DGND DRVDD D13A D12A D11A D10A D9A D8A D7A D6A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9262 CMOS OUTPUTS TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK− Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3 to 5, 9 to 21 D0B to D15B Channel B Data Output Pins. D0B is the LSB and D15B is the MSB. 6, 25, 43 DVDD Digital Supply (1.8 V). 7, 24, 42 DGND Digital Ground. 8, 23, 41 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Overrange Indicator. 26 DCO Data Clock Output. 27 to 40, 44, 45 D0A to D15A Channel A Data Output Pins. D0A is the LSB and D15A is the MSB. 46 ORA Channel A Overrange Indicator. 47 SDIO Serial Port Interface Data Input/Output. 48 SCLK Serial Port Interface Clock. 49 CSB Serial Port Interface Chip Select Active Low. 50 RESET Chip Reset. 51, 62 AGND Analog Ground. 52, 55, 58, 61 AVDD Analog Supply (1.8 V). 53 VIN+A Channel A Analog Input (+). 54 VIN−A Channel A Analog Input (−). 56 VREF Voltage Reference Input. 57 CFILT Noise Limiting Filter Capacitor. 59 VIN+B Channel B Analog Input (+). 60 VIN−B Channel B Analog Input (−). 63 CGND Clock Ground. 64 CLK+ Clock Input (+). 65 (EPAD) Exposed pad (EPAD) Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The exposed pad must be soldered to ground. |
Аналогичный номер детали - AD9262-10EBZ |
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Аналогичное описание - AD9262-10EBZ |
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