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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADM1278-1BCPZ датащи(PDF) 11 Page - Analog Devices |
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ADM1278-1BCPZ датащи(HTML) 11 Page - Analog Devices |
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11 / 61 page  Data Sheet ADM1278 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NOTES 1. NIC = NOT INTERNALLY CONNECTED. 2. SOLDER THE EXPOSED PAD TO THE BOARD TO IMPROVE THERMAL DISSIPATION. THE EXPOSED PAD CAN BE CONNECTED TO GROUND. 1 PSET 2 VCAP 3 ISET 4 ISTART 5 TIMER 6 FAULT 7 ADR1 8 ADR2 24 GATE 23 PGND 22 GND 21 PWGIN 20 VOUT 19 CSOUT 18 PWRGD 17 RETRY ADM1278-1 TOP VIEW (Not to Scale) Figure 4. ADM1278-1 Pin Configuration 1 PSET 2 VCAP 3 ISET 4 ISTART 5 TIMER 6 FAULT 7 ADR1 8 ADR2 24 GATE 23 PGND 22 GND 21 PWGIN 20 VOUT 19 CSOUT 18 PWRGD 17 RETRY ADM1278-3 TOP VIEW (Not to Scale) NOTES 1. NIC = NOT INTERNALLY CONNECTED. 2. SOLDER THE EXPOSED PAD TO THE BOARD TO IMPROVE THERMAL DISSIPATION. THE EXPOSED PAD CAN BE CONNECTED TO GROUND. Figure 5. ADM1278-3 Pin Configuration Table 8. ADM1278-1 and ADM1278-3 Pin Function Descriptions Mnemonic Pin No. ADM1278-1 ADM1278-3 Description 1 PSET PSET Power Limit. This pin allows the constant power limit to be programmed. The current limit is dynamically adjusted to ensure that the maximum power dissipation in the FET never exceeds this limit during any operating condition. The power limit can be adjusted to a user defined value using a resistor divider from VCAP. An external reference can also be used. The FET power is limited to (VPSET × 8)/(50 × RSENSE). 2 VCAP VCAP Internal Regulated Supply. Place a capacitor with a value of 1 µF or greater on this pin to maintain accuracy. This pin can be used as a reference to program the ISET pin voltage. 3 ISET ISET Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a resistor divider from VCAP. An external reference can also be used. 4 ISTART ISTART Start-Up Current Limit. This pin allows a separate start-up current limit to be set for dv/dt power-up mode. When powering up in dv/dt mode, the current charging the capacitor is constant and is typically much smaller than the normal load current. The ISTART pin sets the start-up current limit in a similar manner as ISET is used to set the normal current limit. The start-up current limit is only active while PWRGD is low. The start-up current limit can also be set over PMBus with the STRT_UP_IOUT_LIM register. Start-up current limit = VISET × (STRT_UP_IOUT_LIM/16). The lowest of all the active current limits always takes priority. 5 TIMER TIMER Timer. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The GATE pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold. 6 FAULT FAULT Fault. This pin asserts low and latches after a fault has occurred. The faults that can trigger this pin include an overcurrent fault resulting in the TIMER pin voltage exceeding the upper threshold, an overtemperature fault, and an FET health fault. This is an open-drain output pin. 7, 8 ADR1, ADR2 ADR1, ADR2 PMBus Address. These pins can be tied to GND, tied to VCAP, left floating, or tied low through a resistor for a total of 16 unique PMBus device addresses (see the Device Addressing section). 9, 10, 11 NIC NIC Not Internally Connected. Rev. A | Page 11 of 61 |
Аналогичный номер детали - ADM1278-1BCPZ |
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Аналогичное описание - ADM1278-1BCPZ |
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