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54AC169 датащи(PDF) 3 Page - Texas Instruments

номер детали 54AC169
подробное описание детали  4-Stage Synchronous Bidirectional Counter
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OBSOLETE
54AC169, 54ACT169
www.ti.com
SNOS092B – JULY 1998 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The 'AC/'ACT169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data
input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state
at least a setup time before the rising edge of the clock and remain valid for the recommended hold time
thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode
Select Table. When PE is LOW, the data on the P0–P3 inputs enters the flip-flops on the next rising edge of the
Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input
then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW,
provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 in the Count
Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. If an illegal state
occurs, the 'AC169 will return to the legitimate sequence within two counts. Since the TC signal is derived by
decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC
as a clock signal is not recommended (see logic equations below).
1. Count Enable = CEP •CET • PE
2. Up: TC = Q0•Q1•Q 2Q3•(Up)•CET
3. Down: TC = Q0• Q1•Q2•Q3 •(Down)•CET
Table 1. Mode Select Table(1)
Action on Rising
PE
CEP
CET
U/D
Clock Edge
L
X
X
X
Load (Pn to Qn)
H
L
L
H
Count Up (Increment)
H
L
L
L
Count Down (Decrement)
H
H
X
X
No Change (Hold)
H
X
H
X
No Change (Hold)
(1)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
State Diagrams
Copyright © 1998–2013, Texas Instruments Incorporated
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Product Folder Links: 54AC169 54ACT169


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