54AC11175, 74AC11175

QUADRUPLE DTYPE FLIPFLOPS

WITH CLEAR

SCAS090 − DECEMBER 1989 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Copyright

2−1

Registers, Shift Registers, Pattern

Generators

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

mm Process

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These positive-edge-triggered flipflops implement

D-type flip-flop logic with a direct clear input.

Information at the D inputs that meets the setup

time requirements is transferred to the outputs on

the positive-going edge of the clock pulse. Clock

triggering occurs at a particular voltage level and

is not directly related to the transition time of the

positive-going pulse. When the clock input is at

either the high or low level, the D input signal has

no effect at the output.

The 54AC11175 is characterized for operation

over the full military temperature range of − 55

°C

to 125

°C. The 74AC11175 is characterized for

operation from − 40

°C to 85°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

CLR

CLK

D

Q

Q

L

X

X

L

H

H

↑

HH

L

H

↑

LL

H

H

L

X

Q0

Q0

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1Q

2Q

2Q

GND

GND

GND

GND

3Q

3Q

4Q

1Q

CLR

1D

2D

3D

4D

CLK

4Q

54AC11175 ...J PACKAGE

74AC11175 . . . DW or N PACKAGE

(TOP VIEW)

54AC11014 . . . FK PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4D

CLK

4Q

4Q

3Q

CLR

1Q

1Q

2Q

2Q

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.