74AC11646

OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3STATE OUTPUTS

SCAS079A − JULY 1987 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

2−6

(unless otherwise noted) (see Figure 2)

TA = 25°C

MIN

MAX

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

0

65

0

65

MHz

tw

Pulse duration, CLK high or low

7.7

7.7

ns

tsu

Setup time, A or B before CLKAB

↑ or CLKBA↑

6.5

6.5

ns

th

Hold time, A or B after CLKAB

↑ or CLKBA↑

1

1

ns

(unless otherwise noted) (see Figure 2)

TA = 25°C

MIN

MAX

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

0

100

0

100

MHz

tw

Pulse duration, CLK high or low

5

5

ns

tsu

Setup time, A or B before CLKAB

↑ or CLKBA↑

4.5

4.5

ns

th

Hold time, A or B after CLKAB

↑ or CLKBA↑

1

1

ns

switching characteristics over recommended operating free-air temperature range,

PARAMETER

FROM

TO

TA = 25°C

MIN

MAX

UNIT

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

UNIT

fmax

65

65

MHz

tPLH

A or B

B or A

1.5

9.1

12.1

1.5

13.8

ns

tPHL

A or B

B or A

1.5

10.7

13.4

1.5

14.5

ns

tPZH

OE

A or B

1.5

13

16.4

1.5

18.7

ns

tPZL

OE

A or B

1.5

16.1

20.4

1.5

21.8

ns

tPHZ

OE

A or B

1.5

7.9

9.6

1.5

10.3

ns

tPLZ

OE

A or B

1.5

7.2

8.9

1.5

9.6

ns

tPLH

CLKBA or CLKAB

A or B

1.5

11.8

15

1.5

17

ns

tPHL

CLKBA or CLKAB

A or B

1.5

13.7

16.8

1.5

18.3

ns

tPLH

SBA or SAB†

A or B

1.5

9.8

12.9

1.5

14.4

ns

tPHL

SBA or SAB†

(A or B high)

A or B

1.5

12

14.5

1.5

15.8

ns

tPLH

SBA or SAB†

A or B

1.5

10.7

13.8

1.5

15.4

ns

tPHL

SBA or SAB†

(A or B low)

A or B

1.5

12.4

15

1.5

16.4

ns

tPZH

DIR

A or B

1.5

13.7

17.1

1.5

19.4

ns

tPZL

DIR

A or B

1.5

16.8

21

1.5

23.6

ns

tPHZ

DIR

A or B

1.5

7.9

9.7

1.5

10.5

ns

tPLZ

DIR

A or B

1.5

7.3

9.1

1.5

9.9

ns

† These parameters are measured with the internal output state of the storage register opposite to that of the bus input.