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74ALVCH162721GRE4 датащи(PDF) 1 Page - Texas Instruments

номер детали 74ALVCH162721GRE4
подробное описание детали  3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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74ALVCH162721GRE4 датащи(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)
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OE
Q1
Q2
GND
Q3
Q4
VCC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
NC
CLK
D1
D2
GND
D3
D4
VCC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
CLKEN
NC − No internal connection
SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055G – DECEMBER 1995 – REVISED SEPTEMBER 2004
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-
Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR.
This 20-bit flip-flop is designed for low-voltage 1.65-V
to 3.6-V VCC operation.
The 20 flip-flops of the SN74ALVCH162721 are
edge-triggered D-type flip-flops with qualified clock
storage. On the positive transition of the clock (CLK)
input, the device provides true data at the Q outputs if
the clock-enable (CLKEN) input is low. If CLKEN is
high, no data is stored.
A buffered output-enable (OE) input places the 20
outputs in either a normal logic state (high or low
level)
or
the
high-impedance
state.
In
the
high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without interface or pullup components. OE
does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-
Ω resistors to reduce overshoot and
undershoot.
The SN74ALVCH162721 is characterized for operation from -40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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