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74LVC1G374DCKRG4 датащи(PDF) 1 Page - Texas Instruments |
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74LVC1G374DCKRG4 датащи(HTML) 1 Page - Texas Instruments |
1 / 20 page Seemechanicaldrawingsfordimensions. DBVPACKAGE (TOP VIEW) 3 4 D 2 GND Q OE V CC 6 5 1 CLK DCKPACKAGE (TOP VIEW) OE 3 4 D 2 GND Q 6 5 1 CLK V CC YEP OR YZP PACKAGE (BOTTOMVIEW) OE 2 GND V CC 1 6 CLK D 4 5 3 Q SN74LVC1G374 www.ti.com SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013 Single D-Type Flip-Flop With 3-State Output Check for Samples: SN74LVC1G374 NanoStar™ and NanoFree™ package technology is 1 FEATURES a major breakthrough in IC packaging concepts, 2 • Available in the Texas Instruments NanoStar™ using the die as the package. and NanoFree™ Packages On the positive transition of the clock (CLK) input, the • Supports 5-V VCC Operation Q output is set to the logic level set up at the data (D) • Inputs Accept Voltages to 5.5 V input. • Provides Down Translation to VCC A buffered output-enable (OE) input can be used to • Max tpd of 4 ns at 3.3 V place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the • Low Power Consumption, 10- μA Max ICC high-impedance state, the output neither loads nor • ±24-mA Output Drive at 3.3 V drives the bus lines significantly. The high-impedance • Ioff Supports Live Insertion, Partial-Power- state and increased drive provide the capability to Down Mode, and Back Drive Protection drive bus lines without interface or pullup components. • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II OE does not affect the internal operations of the flip- • ESD Protection Exceeds JESD 22 flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance – 2000-V Human-Body Model (A114-A) state. – 200-V Machine Model (A115-A) To ensure the high-impedance state during power up – 1000-V Charged-Device Model (C101) or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is DESCRIPTION determined by the current-sinking capability of the This single D-type latch is designed for 1.65-V to 5.5- driver. V VCC operation. This device is fully specified for partial-power-down The SN74LVC1G374 features a 3-state output applications using Ioff. The Ioff circuitry disables the designed specifically for driving highly capacitive or outputs, preventing damaging current backflow relatively low-impedance loads. This device is through the device when it is powered down. particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Аналогичный номер детали - 74LVC1G374DCKRG4 |
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Аналогичное описание - 74LVC1G374DCKRG4 |
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