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CDCVF2509A датащи(PDF) 1 Page - Texas Instruments

номер детали CDCVF2509A
подробное описание детали  3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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CDCVF2509A датащи(HTML) 1 Page - Texas Instruments

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CLK
AVCC
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
2G
FBIN
1
2
3
4
5
6
7
8
9
10
11
12
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
1G
FBOUT
24
23
22
21
20
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PW PACKAGE
(TOP VIEW)
CDCVF2509A
www.ti.com
SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH POWER DOWN MODE
Check for Samples: CDCVF2509A
1
FEATURES
25-
Ω On-Chip Series Damping Resistors
Designed to Meet and Exceed PC133
No External RC Network Required
SDRAM Registered DIMM Specification
Operates at 3.3 V
Rev. 1.1
Spread Spectrum Clock Compatible
APPLICATIONS
DRAM Applications
Operating Frequency 20 MHz to 175 MHz
PLL Based Clock Distributors
Static Phase Error Distribution at 66 MHz to
Non-PLL Clock Buffer
166 MHz Is ±125 ps
Jitter (cyc - cyc) at 60 MHz to 175 MHz Is
Typ = 65 ps
Advanced Deep Submicron Process
Results in More Than 40% Lower Power
Consumption Versus Current Generation
PC133 Devices
Auto Frequency Detection to Disable
Device (Power-Down Mode)
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
Separate Output Enable for Each Output
Bank
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
DESCRIPTION
The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is
specifically designed for use with synchronous DRAMs. The CDCVF2509A operates at a 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or
disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase
and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. The device
automatically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into
a low state.
Unlike many products containing PLLs, the CDCVF2509A does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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